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  1. //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file contains the implementation for instruction scheduler function
  10. // pass registry (RegisterScheduler).
  11. //
  12. //===----------------------------------------------------------------------===//
  13.  
  14. #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
  15. #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
  16.  
  17. #include "llvm/CodeGen/MachinePassRegistry.h"
  18. #include "llvm/Support/CodeGen.h"
  19.  
  20. namespace llvm {
  21.  
  22. //===----------------------------------------------------------------------===//
  23. ///
  24. /// RegisterScheduler class - Track the registration of instruction schedulers.
  25. ///
  26. //===----------------------------------------------------------------------===//
  27.  
  28. class ScheduleDAGSDNodes;
  29. class SelectionDAGISel;
  30.  
  31. class RegisterScheduler
  32.     : public MachinePassRegistryNode<
  33.           ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level)> {
  34. public:
  35.   using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*,
  36.                                                    CodeGenOpt::Level);
  37.  
  38.   static MachinePassRegistry<FunctionPassCtor> Registry;
  39.  
  40.   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
  41.       : MachinePassRegistryNode(N, D, C) {
  42.     Registry.Add(this);
  43.   }
  44.   ~RegisterScheduler() { Registry.Remove(this); }
  45.  
  46.  
  47.   // Accessors.
  48.   RegisterScheduler *getNext() const {
  49.     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
  50.   }
  51.  
  52.   static RegisterScheduler *getList() {
  53.     return (RegisterScheduler *)Registry.getList();
  54.   }
  55.  
  56.   static void setListener(MachinePassRegistryListener<FunctionPassCtor> *L) {
  57.     Registry.setListener(L);
  58.   }
  59. };
  60.  
  61. /// createBURRListDAGScheduler - This creates a bottom up register usage
  62. /// reduction list scheduler.
  63. ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
  64.                                                CodeGenOpt::Level OptLevel);
  65.  
  66. /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
  67. /// schedules nodes in source code order when possible.
  68. ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
  69.                                                  CodeGenOpt::Level OptLevel);
  70.  
  71. /// createHybridListDAGScheduler - This creates a bottom up register pressure
  72. /// aware list scheduler that make use of latency information to avoid stalls
  73. /// for long latency instructions in low register pressure mode. In high
  74. /// register pressure mode it schedules to reduce register pressure.
  75. ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
  76.                                                  CodeGenOpt::Level);
  77.  
  78. /// createILPListDAGScheduler - This creates a bottom up register pressure
  79. /// aware list scheduler that tries to increase instruction level parallelism
  80. /// in low register pressure mode. In high register pressure mode it schedules
  81. /// to reduce register pressure.
  82. ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
  83.                                               CodeGenOpt::Level);
  84.  
  85. /// createFastDAGScheduler - This creates a "fast" scheduler.
  86. ///
  87. ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
  88.                                            CodeGenOpt::Level OptLevel);
  89.  
  90. /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
  91. /// DFA driven list scheduler with clustering heuristic to control
  92. /// register pressure.
  93. ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
  94.                                            CodeGenOpt::Level OptLevel);
  95. /// createDefaultScheduler - This creates an instruction scheduler appropriate
  96. /// for the target.
  97. ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
  98.                                            CodeGenOpt::Level OptLevel);
  99.  
  100. /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
  101. /// linearize the DAG using topological order.
  102. ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
  103.                                         CodeGenOpt::Level OptLevel);
  104.  
  105. } // end namespace llvm
  106.  
  107. #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H
  108.