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  1. //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file contains the declaration of the MachineInstr class, which is the
  10. // basic representation for all target dependent machine instructions used by
  11. // the back end.
  12. //
  13. //===----------------------------------------------------------------------===//
  14.  
  15. #ifndef LLVM_CODEGEN_MACHINEINSTR_H
  16. #define LLVM_CODEGEN_MACHINEINSTR_H
  17.  
  18. #include "llvm/ADT/DenseMapInfo.h"
  19. #include "llvm/ADT/PointerSumType.h"
  20. #include "llvm/ADT/SmallSet.h"
  21. #include "llvm/ADT/ilist.h"
  22. #include "llvm/ADT/ilist_node.h"
  23. #include "llvm/ADT/iterator_range.h"
  24. #include "llvm/CodeGen/MachineMemOperand.h"
  25. #include "llvm/CodeGen/MachineOperand.h"
  26. #include "llvm/CodeGen/TargetOpcodes.h"
  27. #include "llvm/IR/DebugLoc.h"
  28. #include "llvm/IR/InlineAsm.h"
  29. #include "llvm/MC/MCInstrDesc.h"
  30. #include "llvm/MC/MCSymbol.h"
  31. #include "llvm/Support/ArrayRecycler.h"
  32. #include "llvm/Support/TrailingObjects.h"
  33. #include <algorithm>
  34. #include <cassert>
  35. #include <cstdint>
  36. #include <utility>
  37.  
  38. namespace llvm {
  39.  
  40. class DILabel;
  41. class Instruction;
  42. class MDNode;
  43. class AAResults;
  44. template <typename T> class ArrayRef;
  45. class DIExpression;
  46. class DILocalVariable;
  47. class MachineBasicBlock;
  48. class MachineFunction;
  49. class MachineRegisterInfo;
  50. class ModuleSlotTracker;
  51. class raw_ostream;
  52. template <typename T> class SmallVectorImpl;
  53. class SmallBitVector;
  54. class StringRef;
  55. class TargetInstrInfo;
  56. class TargetRegisterClass;
  57. class TargetRegisterInfo;
  58.  
  59. //===----------------------------------------------------------------------===//
  60. /// Representation of each machine instruction.
  61. ///
  62. /// This class isn't a POD type, but it must have a trivial destructor. When a
  63. /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
  64. /// without having their destructor called.
  65. ///
  66. class MachineInstr
  67.     : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
  68.                                     ilist_sentinel_tracking<true>> {
  69. public:
  70.   using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
  71.  
  72.   /// Flags to specify different kinds of comments to output in
  73.   /// assembly code.  These flags carry semantic information not
  74.   /// otherwise easily derivable from the IR text.
  75.   ///
  76.   enum CommentFlag {
  77.     ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
  78.     NoSchedComment = 0x2,
  79.     TAsmComments = 0x4    // Target Asm comments should start from this value.
  80.   };
  81.  
  82.   enum MIFlag {
  83.     NoFlags      = 0,
  84.     FrameSetup   = 1 << 0,              // Instruction is used as a part of
  85.                                         // function frame setup code.
  86.     FrameDestroy = 1 << 1,              // Instruction is used as a part of
  87.                                         // function frame destruction code.
  88.     BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
  89.     BundledSucc  = 1 << 3,              // Instruction has bundled successors.
  90.     FmNoNans     = 1 << 4,              // Instruction does not support Fast
  91.                                         // math nan values.
  92.     FmNoInfs     = 1 << 5,              // Instruction does not support Fast
  93.                                         // math infinity values.
  94.     FmNsz        = 1 << 6,              // Instruction is not required to retain
  95.                                         // signed zero values.
  96.     FmArcp       = 1 << 7,              // Instruction supports Fast math
  97.                                         // reciprocal approximations.
  98.     FmContract   = 1 << 8,              // Instruction supports Fast math
  99.                                         // contraction operations like fma.
  100.     FmAfn        = 1 << 9,              // Instruction may map to Fast math
  101.                                         // intrinsic approximation.
  102.     FmReassoc    = 1 << 10,             // Instruction supports Fast math
  103.                                         // reassociation of operand order.
  104.     NoUWrap      = 1 << 11,             // Instruction supports binary operator
  105.                                         // no unsigned wrap.
  106.     NoSWrap      = 1 << 12,             // Instruction supports binary operator
  107.                                         // no signed wrap.
  108.     IsExact      = 1 << 13,             // Instruction supports division is
  109.                                         // known to be exact.
  110.     NoFPExcept   = 1 << 14,             // Instruction does not raise
  111.                                         // floatint-point exceptions.
  112.     NoMerge      = 1 << 15,             // Passes that drop source location info
  113.                                         // (e.g. branch folding) should skip
  114.                                         // this instruction.
  115.   };
  116.  
  117. private:
  118.   const MCInstrDesc *MCID;              // Instruction descriptor.
  119.   MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
  120.  
  121.   // Operands are allocated by an ArrayRecycler.
  122.   MachineOperand *Operands = nullptr;   // Pointer to the first operand.
  123.   unsigned NumOperands = 0;             // Number of operands on instruction.
  124.  
  125.   uint16_t Flags = 0;                   // Various bits of additional
  126.                                         // information about machine
  127.                                         // instruction.
  128.  
  129.   uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
  130.                                         // the AsmPrinter to emit helpful
  131.                                         // comments.  This is *not* semantic
  132.                                         // information.  Do not use this for
  133.                                         // anything other than to convey comment
  134.                                         // information to AsmPrinter.
  135.  
  136.   // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
  137.   // to properly pack.
  138.   using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
  139.   OperandCapacity CapOperands;          // Capacity of the Operands array.
  140.  
  141.   /// Internal implementation detail class that provides out-of-line storage for
  142.   /// extra info used by the machine instruction when this info cannot be stored
  143.   /// in-line within the instruction itself.
  144.   ///
  145.   /// This has to be defined eagerly due to the implementation constraints of
  146.   /// `PointerSumType` where it is used.
  147.   class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
  148.                                           MCSymbol *, MDNode *, uint32_t> {
  149.   public:
  150.     static ExtraInfo *create(BumpPtrAllocator &Allocator,
  151.                              ArrayRef<MachineMemOperand *> MMOs,
  152.                              MCSymbol *PreInstrSymbol = nullptr,
  153.                              MCSymbol *PostInstrSymbol = nullptr,
  154.                              MDNode *HeapAllocMarker = nullptr,
  155.                              MDNode *PCSections = nullptr,
  156.                              uint32_t CFIType = 0) {
  157.       bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
  158.       bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
  159.       bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
  160.       bool HasCFIType = CFIType != 0;
  161.       bool HasPCSections = PCSections != nullptr;
  162.       auto *Result = new (Allocator.Allocate(
  163.           totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
  164.               MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
  165.               HasHeapAllocMarker + HasPCSections, HasCFIType),
  166.           alignof(ExtraInfo)))
  167.           ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
  168.                     HasHeapAllocMarker, HasPCSections, HasCFIType);
  169.  
  170.       // Copy the actual data into the trailing objects.
  171.       std::copy(MMOs.begin(), MMOs.end(),
  172.                 Result->getTrailingObjects<MachineMemOperand *>());
  173.  
  174.       if (HasPreInstrSymbol)
  175.         Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
  176.       if (HasPostInstrSymbol)
  177.         Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
  178.             PostInstrSymbol;
  179.       if (HasHeapAllocMarker)
  180.         Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
  181.       if (HasPCSections)
  182.         Result->getTrailingObjects<MDNode *>()[HasHeapAllocMarker] =
  183.             PCSections;
  184.       if (HasCFIType)
  185.         Result->getTrailingObjects<uint32_t>()[0] = CFIType;
  186.  
  187.       return Result;
  188.     }
  189.  
  190.     ArrayRef<MachineMemOperand *> getMMOs() const {
  191.       return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
  192.     }
  193.  
  194.     MCSymbol *getPreInstrSymbol() const {
  195.       return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
  196.     }
  197.  
  198.     MCSymbol *getPostInstrSymbol() const {
  199.       return HasPostInstrSymbol
  200.                  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
  201.                  : nullptr;
  202.     }
  203.  
  204.     MDNode *getHeapAllocMarker() const {
  205.       return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
  206.     }
  207.  
  208.     MDNode *getPCSections() const {
  209.       return HasPCSections
  210.                  ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
  211.                  : nullptr;
  212.     }
  213.  
  214.     uint32_t getCFIType() const {
  215.       return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
  216.     }
  217.  
  218.   private:
  219.     friend TrailingObjects;
  220.  
  221.     // Description of the extra info, used to interpret the actual optional
  222.     // data appended.
  223.     //
  224.     // Note that this is not terribly space optimized. This leaves a great deal
  225.     // of flexibility to fit more in here later.
  226.     const int NumMMOs;
  227.     const bool HasPreInstrSymbol;
  228.     const bool HasPostInstrSymbol;
  229.     const bool HasHeapAllocMarker;
  230.     const bool HasPCSections;
  231.     const bool HasCFIType;
  232.  
  233.     // Implement the `TrailingObjects` internal API.
  234.     size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
  235.       return NumMMOs;
  236.     }
  237.     size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
  238.       return HasPreInstrSymbol + HasPostInstrSymbol;
  239.     }
  240.     size_t numTrailingObjects(OverloadToken<MDNode *>) const {
  241.       return HasHeapAllocMarker + HasPCSections;
  242.     }
  243.     size_t numTrailingObjects(OverloadToken<uint32_t>) const {
  244.       return HasCFIType;
  245.     }
  246.  
  247.     // Just a boring constructor to allow us to initialize the sizes. Always use
  248.     // the `create` routine above.
  249.     ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
  250.               bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType)
  251.         : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
  252.           HasPostInstrSymbol(HasPostInstrSymbol),
  253.           HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
  254.           HasCFIType(HasCFIType) {}
  255.   };
  256.  
  257.   /// Enumeration of the kinds of inline extra info available. It is important
  258.   /// that the `MachineMemOperand` inline kind has a tag value of zero to make
  259.   /// it accessible as an `ArrayRef`.
  260.   enum ExtraInfoInlineKinds {
  261.     EIIK_MMO = 0,
  262.     EIIK_PreInstrSymbol,
  263.     EIIK_PostInstrSymbol,
  264.     EIIK_OutOfLine
  265.   };
  266.  
  267.   // We store extra information about the instruction here. The common case is
  268.   // expected to be nothing or a single pointer (typically a MMO or a symbol).
  269.   // We work to optimize this common case by storing it inline here rather than
  270.   // requiring a separate allocation, but we fall back to an allocation when
  271.   // multiple pointers are needed.
  272.   PointerSumType<ExtraInfoInlineKinds,
  273.                  PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
  274.                  PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
  275.                  PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
  276.                  PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
  277.       Info;
  278.  
  279.   DebugLoc DbgLoc; // Source line information.
  280.  
  281.   /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
  282.   /// defined by this instruction.
  283.   unsigned DebugInstrNum;
  284.  
  285.   // Intrusive list support
  286.   friend struct ilist_traits<MachineInstr>;
  287.   friend struct ilist_callback_traits<MachineBasicBlock>;
  288.   void setParent(MachineBasicBlock *P) { Parent = P; }
  289.  
  290.   /// This constructor creates a copy of the given
  291.   /// MachineInstr in the given MachineFunction.
  292.   MachineInstr(MachineFunction &, const MachineInstr &);
  293.  
  294.   /// This constructor create a MachineInstr and add the implicit operands.
  295.   /// It reserves space for number of operands specified by
  296.   /// MCInstrDesc.  An explicit DebugLoc is supplied.
  297.   MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
  298.                bool NoImp = false);
  299.  
  300.   // MachineInstrs are pool-allocated and owned by MachineFunction.
  301.   friend class MachineFunction;
  302.  
  303.   void
  304.   dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
  305.             SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
  306.  
  307. public:
  308.   MachineInstr(const MachineInstr &) = delete;
  309.   MachineInstr &operator=(const MachineInstr &) = delete;
  310.   // Use MachineFunction::DeleteMachineInstr() instead.
  311.   ~MachineInstr() = delete;
  312.  
  313.   const MachineBasicBlock* getParent() const { return Parent; }
  314.   MachineBasicBlock* getParent() { return Parent; }
  315.  
  316.   /// Move the instruction before \p MovePos.
  317.   void moveBefore(MachineInstr *MovePos);
  318.  
  319.   /// Return the function that contains the basic block that this instruction
  320.   /// belongs to.
  321.   ///
  322.   /// Note: this is undefined behaviour if the instruction does not have a
  323.   /// parent.
  324.   const MachineFunction *getMF() const;
  325.   MachineFunction *getMF() {
  326.     return const_cast<MachineFunction *>(
  327.         static_cast<const MachineInstr *>(this)->getMF());
  328.   }
  329.  
  330.   /// Return the asm printer flags bitvector.
  331.   uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
  332.  
  333.   /// Clear the AsmPrinter bitvector.
  334.   void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
  335.  
  336.   /// Return whether an AsmPrinter flag is set.
  337.   bool getAsmPrinterFlag(CommentFlag Flag) const {
  338.     return AsmPrinterFlags & Flag;
  339.   }
  340.  
  341.   /// Set a flag for the AsmPrinter.
  342.   void setAsmPrinterFlag(uint8_t Flag) {
  343.     AsmPrinterFlags |= Flag;
  344.   }
  345.  
  346.   /// Clear specific AsmPrinter flags.
  347.   void clearAsmPrinterFlag(CommentFlag Flag) {
  348.     AsmPrinterFlags &= ~Flag;
  349.   }
  350.  
  351.   /// Return the MI flags bitvector.
  352.   uint16_t getFlags() const {
  353.     return Flags;
  354.   }
  355.  
  356.   /// Return whether an MI flag is set.
  357.   bool getFlag(MIFlag Flag) const {
  358.     return Flags & Flag;
  359.   }
  360.  
  361.   /// Set a MI flag.
  362.   void setFlag(MIFlag Flag) {
  363.     Flags |= (uint16_t)Flag;
  364.   }
  365.  
  366.   void setFlags(unsigned flags) {
  367.     // Filter out the automatically maintained flags.
  368.     unsigned Mask = BundledPred | BundledSucc;
  369.     Flags = (Flags & Mask) | (flags & ~Mask);
  370.   }
  371.  
  372.   /// clearFlag - Clear a MI flag.
  373.   void clearFlag(MIFlag Flag) {
  374.     Flags &= ~((uint16_t)Flag);
  375.   }
  376.  
  377.   /// Return true if MI is in a bundle (but not the first MI in a bundle).
  378.   ///
  379.   /// A bundle looks like this before it's finalized:
  380.   ///   ----------------
  381.   ///   |      MI      |
  382.   ///   ----------------
  383.   ///          |
  384.   ///   ----------------
  385.   ///   |      MI    * |
  386.   ///   ----------------
  387.   ///          |
  388.   ///   ----------------
  389.   ///   |      MI    * |
  390.   ///   ----------------
  391.   /// In this case, the first MI starts a bundle but is not inside a bundle, the
  392.   /// next 2 MIs are considered "inside" the bundle.
  393.   ///
  394.   /// After a bundle is finalized, it looks like this:
  395.   ///   ----------------
  396.   ///   |    Bundle    |
  397.   ///   ----------------
  398.   ///          |
  399.   ///   ----------------
  400.   ///   |      MI    * |
  401.   ///   ----------------
  402.   ///          |
  403.   ///   ----------------
  404.   ///   |      MI    * |
  405.   ///   ----------------
  406.   ///          |
  407.   ///   ----------------
  408.   ///   |      MI    * |
  409.   ///   ----------------
  410.   /// The first instruction has the special opcode "BUNDLE". It's not "inside"
  411.   /// a bundle, but the next three MIs are.
  412.   bool isInsideBundle() const {
  413.     return getFlag(BundledPred);
  414.   }
  415.  
  416.   /// Return true if this instruction part of a bundle. This is true
  417.   /// if either itself or its following instruction is marked "InsideBundle".
  418.   bool isBundled() const {
  419.     return isBundledWithPred() || isBundledWithSucc();
  420.   }
  421.  
  422.   /// Return true if this instruction is part of a bundle, and it is not the
  423.   /// first instruction in the bundle.
  424.   bool isBundledWithPred() const { return getFlag(BundledPred); }
  425.  
  426.   /// Return true if this instruction is part of a bundle, and it is not the
  427.   /// last instruction in the bundle.
  428.   bool isBundledWithSucc() const { return getFlag(BundledSucc); }
  429.  
  430.   /// Bundle this instruction with its predecessor. This can be an unbundled
  431.   /// instruction, or it can be the first instruction in a bundle.
  432.   void bundleWithPred();
  433.  
  434.   /// Bundle this instruction with its successor. This can be an unbundled
  435.   /// instruction, or it can be the last instruction in a bundle.
  436.   void bundleWithSucc();
  437.  
  438.   /// Break bundle above this instruction.
  439.   void unbundleFromPred();
  440.  
  441.   /// Break bundle below this instruction.
  442.   void unbundleFromSucc();
  443.  
  444.   /// Returns the debug location id of this MachineInstr.
  445.   const DebugLoc &getDebugLoc() const { return DbgLoc; }
  446.  
  447.   /// Return the operand containing the offset to be used if this DBG_VALUE
  448.   /// instruction is indirect; will be an invalid register if this value is
  449.   /// not indirect, and an immediate with value 0 otherwise.
  450.   const MachineOperand &getDebugOffset() const {
  451.     assert(isNonListDebugValue() && "not a DBG_VALUE");
  452.     return getOperand(1);
  453.   }
  454.   MachineOperand &getDebugOffset() {
  455.     assert(isNonListDebugValue() && "not a DBG_VALUE");
  456.     return getOperand(1);
  457.   }
  458.  
  459.   /// Return the operand for the debug variable referenced by
  460.   /// this DBG_VALUE instruction.
  461.   const MachineOperand &getDebugVariableOp() const;
  462.   MachineOperand &getDebugVariableOp();
  463.  
  464.   /// Return the debug variable referenced by
  465.   /// this DBG_VALUE instruction.
  466.   const DILocalVariable *getDebugVariable() const;
  467.  
  468.   /// Return the operand for the complex address expression referenced by
  469.   /// this DBG_VALUE instruction.
  470.   const MachineOperand &getDebugExpressionOp() const;
  471.   MachineOperand &getDebugExpressionOp();
  472.  
  473.   /// Return the complex address expression referenced by
  474.   /// this DBG_VALUE instruction.
  475.   const DIExpression *getDebugExpression() const;
  476.  
  477.   /// Return the debug label referenced by
  478.   /// this DBG_LABEL instruction.
  479.   const DILabel *getDebugLabel() const;
  480.  
  481.   /// Fetch the instruction number of this MachineInstr. If it does not have
  482.   /// one already, a new and unique number will be assigned.
  483.   unsigned getDebugInstrNum();
  484.  
  485.   /// Fetch instruction number of this MachineInstr -- but before it's inserted
  486.   /// into \p MF. Needed for transformations that create an instruction but
  487.   /// don't immediately insert them.
  488.   unsigned getDebugInstrNum(MachineFunction &MF);
  489.  
  490.   /// Examine the instruction number of this MachineInstr. May be zero if
  491.   /// it hasn't been assigned a number yet.
  492.   unsigned peekDebugInstrNum() const { return DebugInstrNum; }
  493.  
  494.   /// Set instruction number of this MachineInstr. Avoid using unless you're
  495.   /// deserializing this information.
  496.   void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
  497.  
  498.   /// Drop any variable location debugging information associated with this
  499.   /// instruction. Use when an instruction is modified in such a way that it no
  500.   /// longer defines the value it used to. Variable locations using that value
  501.   /// will be dropped.
  502.   void dropDebugNumber() { DebugInstrNum = 0; }
  503.  
  504.   /// Emit an error referring to the source location of this instruction.
  505.   /// This should only be used for inline assembly that is somehow
  506.   /// impossible to compile. Other errors should have been handled much
  507.   /// earlier.
  508.   ///
  509.   /// If this method returns, the caller should try to recover from the error.
  510.   void emitError(StringRef Msg) const;
  511.  
  512.   /// Returns the target instruction descriptor of this MachineInstr.
  513.   const MCInstrDesc &getDesc() const { return *MCID; }
  514.  
  515.   /// Returns the opcode of this MachineInstr.
  516.   unsigned getOpcode() const { return MCID->Opcode; }
  517.  
  518.   /// Retuns the total number of operands.
  519.   unsigned getNumOperands() const { return NumOperands; }
  520.  
  521.   /// Returns the total number of operands which are debug locations.
  522.   unsigned getNumDebugOperands() const {
  523.     return std::distance(debug_operands().begin(), debug_operands().end());
  524.   }
  525.  
  526.   const MachineOperand& getOperand(unsigned i) const {
  527.     assert(i < getNumOperands() && "getOperand() out of range!");
  528.     return Operands[i];
  529.   }
  530.   MachineOperand& getOperand(unsigned i) {
  531.     assert(i < getNumOperands() && "getOperand() out of range!");
  532.     return Operands[i];
  533.   }
  534.  
  535.   MachineOperand &getDebugOperand(unsigned Index) {
  536.     assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
  537.     return *(debug_operands().begin() + Index);
  538.   }
  539.   const MachineOperand &getDebugOperand(unsigned Index) const {
  540.     assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
  541.     return *(debug_operands().begin() + Index);
  542.   }
  543.  
  544.   SmallSet<Register, 4> getUsedDebugRegs() const {
  545.     assert(isDebugValue() && "not a DBG_VALUE*");
  546.     SmallSet<Register, 4> UsedRegs;
  547.     for (const auto &MO : debug_operands())
  548.       if (MO.isReg() && MO.getReg())
  549.         UsedRegs.insert(MO.getReg());
  550.     return UsedRegs;
  551.   }
  552.  
  553.   /// Returns whether this debug value has at least one debug operand with the
  554.   /// register \p Reg.
  555.   bool hasDebugOperandForReg(Register Reg) const {
  556.     return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
  557.       return Op.isReg() && Op.getReg() == Reg;
  558.     });
  559.   }
  560.  
  561.   /// Returns a range of all of the operands that correspond to a debug use of
  562.   /// \p Reg.
  563.   template <typename Operand, typename Instruction>
  564.   static iterator_range<
  565.       filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
  566.   getDebugOperandsForReg(Instruction *MI, Register Reg) {
  567.     std::function<bool(Operand & Op)> OpUsesReg(
  568.         [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
  569.     return make_filter_range(MI->debug_operands(), OpUsesReg);
  570.   }
  571.   iterator_range<filter_iterator<const MachineOperand *,
  572.                                  std::function<bool(const MachineOperand &Op)>>>
  573.   getDebugOperandsForReg(Register Reg) const {
  574.     return MachineInstr::getDebugOperandsForReg<const MachineOperand,
  575.                                                 const MachineInstr>(this, Reg);
  576.   }
  577.   iterator_range<filter_iterator<MachineOperand *,
  578.                                  std::function<bool(MachineOperand &Op)>>>
  579.   getDebugOperandsForReg(Register Reg) {
  580.     return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
  581.         this, Reg);
  582.   }
  583.  
  584.   bool isDebugOperand(const MachineOperand *Op) const {
  585.     return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
  586.   }
  587.  
  588.   unsigned getDebugOperandIndex(const MachineOperand *Op) const {
  589.     assert(isDebugOperand(Op) && "Expected a debug operand.");
  590.     return std::distance(adl_begin(debug_operands()), Op);
  591.   }
  592.  
  593.   /// Returns the total number of definitions.
  594.   unsigned getNumDefs() const {
  595.     return getNumExplicitDefs() + MCID->implicit_defs().size();
  596.   }
  597.  
  598.   /// Returns true if the instruction has implicit definition.
  599.   bool hasImplicitDef() const {
  600.     for (const MachineOperand &MO : implicit_operands())
  601.       if (MO.isDef() && MO.isImplicit())
  602.         return true;
  603.     return false;
  604.   }
  605.  
  606.   /// Returns the implicit operands number.
  607.   unsigned getNumImplicitOperands() const {
  608.     return getNumOperands() - getNumExplicitOperands();
  609.   }
  610.  
  611.   /// Return true if operand \p OpIdx is a subregister index.
  612.   bool isOperandSubregIdx(unsigned OpIdx) const {
  613.     assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
  614.     if (isExtractSubreg() && OpIdx == 2)
  615.       return true;
  616.     if (isInsertSubreg() && OpIdx == 3)
  617.       return true;
  618.     if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
  619.       return true;
  620.     if (isSubregToReg() && OpIdx == 3)
  621.       return true;
  622.     return false;
  623.   }
  624.  
  625.   /// Returns the number of non-implicit operands.
  626.   unsigned getNumExplicitOperands() const;
  627.  
  628.   /// Returns the number of non-implicit definitions.
  629.   unsigned getNumExplicitDefs() const;
  630.  
  631.   /// iterator/begin/end - Iterate over all operands of a machine instruction.
  632.   using mop_iterator = MachineOperand *;
  633.   using const_mop_iterator = const MachineOperand *;
  634.  
  635.   mop_iterator operands_begin() { return Operands; }
  636.   mop_iterator operands_end() { return Operands + NumOperands; }
  637.  
  638.   const_mop_iterator operands_begin() const { return Operands; }
  639.   const_mop_iterator operands_end() const { return Operands + NumOperands; }
  640.  
  641.   iterator_range<mop_iterator> operands() {
  642.     return make_range(operands_begin(), operands_end());
  643.   }
  644.   iterator_range<const_mop_iterator> operands() const {
  645.     return make_range(operands_begin(), operands_end());
  646.   }
  647.   iterator_range<mop_iterator> explicit_operands() {
  648.     return make_range(operands_begin(),
  649.                       operands_begin() + getNumExplicitOperands());
  650.   }
  651.   iterator_range<const_mop_iterator> explicit_operands() const {
  652.     return make_range(operands_begin(),
  653.                       operands_begin() + getNumExplicitOperands());
  654.   }
  655.   iterator_range<mop_iterator> implicit_operands() {
  656.     return make_range(explicit_operands().end(), operands_end());
  657.   }
  658.   iterator_range<const_mop_iterator> implicit_operands() const {
  659.     return make_range(explicit_operands().end(), operands_end());
  660.   }
  661.   /// Returns a range over all operands that are used to determine the variable
  662.   /// location for this DBG_VALUE instruction.
  663.   iterator_range<mop_iterator> debug_operands() {
  664.     assert((isDebugValueLike()) && "Must be a debug value instruction.");
  665.     return isNonListDebugValue()
  666.                ? make_range(operands_begin(), operands_begin() + 1)
  667.                : make_range(operands_begin() + 2, operands_end());
  668.   }
  669.   /// \copydoc debug_operands()
  670.   iterator_range<const_mop_iterator> debug_operands() const {
  671.     assert((isDebugValueLike()) && "Must be a debug value instruction.");
  672.     return isNonListDebugValue()
  673.                ? make_range(operands_begin(), operands_begin() + 1)
  674.                : make_range(operands_begin() + 2, operands_end());
  675.   }
  676.   /// Returns a range over all explicit operands that are register definitions.
  677.   /// Implicit definition are not included!
  678.   iterator_range<mop_iterator> defs() {
  679.     return make_range(operands_begin(),
  680.                       operands_begin() + getNumExplicitDefs());
  681.   }
  682.   /// \copydoc defs()
  683.   iterator_range<const_mop_iterator> defs() const {
  684.     return make_range(operands_begin(),
  685.                       operands_begin() + getNumExplicitDefs());
  686.   }
  687.   /// Returns a range that includes all operands that are register uses.
  688.   /// This may include unrelated operands which are not register uses.
  689.   iterator_range<mop_iterator> uses() {
  690.     return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
  691.   }
  692.   /// \copydoc uses()
  693.   iterator_range<const_mop_iterator> uses() const {
  694.     return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
  695.   }
  696.   iterator_range<mop_iterator> explicit_uses() {
  697.     return make_range(operands_begin() + getNumExplicitDefs(),
  698.                       operands_begin() + getNumExplicitOperands());
  699.   }
  700.   iterator_range<const_mop_iterator> explicit_uses() const {
  701.     return make_range(operands_begin() + getNumExplicitDefs(),
  702.                       operands_begin() + getNumExplicitOperands());
  703.   }
  704.  
  705.   /// Returns the number of the operand iterator \p I points to.
  706.   unsigned getOperandNo(const_mop_iterator I) const {
  707.     return I - operands_begin();
  708.   }
  709.  
  710.   /// Access to memory operands of the instruction. If there are none, that does
  711.   /// not imply anything about whether the function accesses memory. Instead,
  712.   /// the caller must behave conservatively.
  713.   ArrayRef<MachineMemOperand *> memoperands() const {
  714.     if (!Info)
  715.       return {};
  716.  
  717.     if (Info.is<EIIK_MMO>())
  718.       return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
  719.  
  720.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  721.       return EI->getMMOs();
  722.  
  723.     return {};
  724.   }
  725.  
  726.   /// Access to memory operands of the instruction.
  727.   ///
  728.   /// If `memoperands_begin() == memoperands_end()`, that does not imply
  729.   /// anything about whether the function accesses memory. Instead, the caller
  730.   /// must behave conservatively.
  731.   mmo_iterator memoperands_begin() const { return memoperands().begin(); }
  732.  
  733.   /// Access to memory operands of the instruction.
  734.   ///
  735.   /// If `memoperands_begin() == memoperands_end()`, that does not imply
  736.   /// anything about whether the function accesses memory. Instead, the caller
  737.   /// must behave conservatively.
  738.   mmo_iterator memoperands_end() const { return memoperands().end(); }
  739.  
  740.   /// Return true if we don't have any memory operands which described the
  741.   /// memory access done by this instruction.  If this is true, calling code
  742.   /// must be conservative.
  743.   bool memoperands_empty() const { return memoperands().empty(); }
  744.  
  745.   /// Return true if this instruction has exactly one MachineMemOperand.
  746.   bool hasOneMemOperand() const { return memoperands().size() == 1; }
  747.  
  748.   /// Return the number of memory operands.
  749.   unsigned getNumMemOperands() const { return memoperands().size(); }
  750.  
  751.   /// Helper to extract a pre-instruction symbol if one has been added.
  752.   MCSymbol *getPreInstrSymbol() const {
  753.     if (!Info)
  754.       return nullptr;
  755.     if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
  756.       return S;
  757.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  758.       return EI->getPreInstrSymbol();
  759.  
  760.     return nullptr;
  761.   }
  762.  
  763.   /// Helper to extract a post-instruction symbol if one has been added.
  764.   MCSymbol *getPostInstrSymbol() const {
  765.     if (!Info)
  766.       return nullptr;
  767.     if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
  768.       return S;
  769.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  770.       return EI->getPostInstrSymbol();
  771.  
  772.     return nullptr;
  773.   }
  774.  
  775.   /// Helper to extract a heap alloc marker if one has been added.
  776.   MDNode *getHeapAllocMarker() const {
  777.     if (!Info)
  778.       return nullptr;
  779.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  780.       return EI->getHeapAllocMarker();
  781.  
  782.     return nullptr;
  783.   }
  784.  
  785.   /// Helper to extract PCSections metadata target sections.
  786.   MDNode *getPCSections() const {
  787.     if (!Info)
  788.       return nullptr;
  789.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  790.       return EI->getPCSections();
  791.  
  792.     return nullptr;
  793.   }
  794.  
  795.   /// Helper to extract a CFI type hash if one has been added.
  796.   uint32_t getCFIType() const {
  797.     if (!Info)
  798.       return 0;
  799.     if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
  800.       return EI->getCFIType();
  801.  
  802.     return 0;
  803.   }
  804.  
  805.   /// API for querying MachineInstr properties. They are the same as MCInstrDesc
  806.   /// queries but they are bundle aware.
  807.  
  808.   enum QueryType {
  809.     IgnoreBundle,    // Ignore bundles
  810.     AnyInBundle,     // Return true if any instruction in bundle has property
  811.     AllInBundle      // Return true if all instructions in bundle have property
  812.   };
  813.  
  814.   /// Return true if the instruction (or in the case of a bundle,
  815.   /// the instructions inside the bundle) has the specified property.
  816.   /// The first argument is the property being queried.
  817.   /// The second argument indicates whether the query should look inside
  818.   /// instruction bundles.
  819.   bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
  820.     assert(MCFlag < 64 &&
  821.            "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
  822.     // Inline the fast path for unbundled or bundle-internal instructions.
  823.     if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
  824.       return getDesc().getFlags() & (1ULL << MCFlag);
  825.  
  826.     // If this is the first instruction in a bundle, take the slow path.
  827.     return hasPropertyInBundle(1ULL << MCFlag, Type);
  828.   }
  829.  
  830.   /// Return true if this is an instruction that should go through the usual
  831.   /// legalization steps.
  832.   bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
  833.     return hasProperty(MCID::PreISelOpcode, Type);
  834.   }
  835.  
  836.   /// Return true if this instruction can have a variable number of operands.
  837.   /// In this case, the variable operands will be after the normal
  838.   /// operands but before the implicit definitions and uses (if any are
  839.   /// present).
  840.   bool isVariadic(QueryType Type = IgnoreBundle) const {
  841.     return hasProperty(MCID::Variadic, Type);
  842.   }
  843.  
  844.   /// Set if this instruction has an optional definition, e.g.
  845.   /// ARM instructions which can set condition code if 's' bit is set.
  846.   bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
  847.     return hasProperty(MCID::HasOptionalDef, Type);
  848.   }
  849.  
  850.   /// Return true if this is a pseudo instruction that doesn't
  851.   /// correspond to a real machine instruction.
  852.   bool isPseudo(QueryType Type = IgnoreBundle) const {
  853.     return hasProperty(MCID::Pseudo, Type);
  854.   }
  855.  
  856.   /// Return true if this instruction doesn't produce any output in the form of
  857.   /// executable instructions.
  858.   bool isMetaInstruction(QueryType Type = IgnoreBundle) const {
  859.     return hasProperty(MCID::Meta, Type);
  860.   }
  861.  
  862.   bool isReturn(QueryType Type = AnyInBundle) const {
  863.     return hasProperty(MCID::Return, Type);
  864.   }
  865.  
  866.   /// Return true if this is an instruction that marks the end of an EH scope,
  867.   /// i.e., a catchpad or a cleanuppad instruction.
  868.   bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
  869.     return hasProperty(MCID::EHScopeReturn, Type);
  870.   }
  871.  
  872.   bool isCall(QueryType Type = AnyInBundle) const {
  873.     return hasProperty(MCID::Call, Type);
  874.   }
  875.  
  876.   /// Return true if this is a call instruction that may have an associated
  877.   /// call site entry in the debug info.
  878.   bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
  879.   /// Return true if copying, moving, or erasing this instruction requires
  880.   /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
  881.   /// \ref eraseCallSiteInfo).
  882.   bool shouldUpdateCallSiteInfo() const;
  883.  
  884.   /// Returns true if the specified instruction stops control flow
  885.   /// from executing the instruction immediately following it.  Examples include
  886.   /// unconditional branches and return instructions.
  887.   bool isBarrier(QueryType Type = AnyInBundle) const {
  888.     return hasProperty(MCID::Barrier, Type);
  889.   }
  890.  
  891.   /// Returns true if this instruction part of the terminator for a basic block.
  892.   /// Typically this is things like return and branch instructions.
  893.   ///
  894.   /// Various passes use this to insert code into the bottom of a basic block,
  895.   /// but before control flow occurs.
  896.   bool isTerminator(QueryType Type = AnyInBundle) const {
  897.     return hasProperty(MCID::Terminator, Type);
  898.   }
  899.  
  900.   /// Returns true if this is a conditional, unconditional, or indirect branch.
  901.   /// Predicates below can be used to discriminate between
  902.   /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
  903.   /// get more information.
  904.   bool isBranch(QueryType Type = AnyInBundle) const {
  905.     return hasProperty(MCID::Branch, Type);
  906.   }
  907.  
  908.   /// Return true if this is an indirect branch, such as a
  909.   /// branch through a register.
  910.   bool isIndirectBranch(QueryType Type = AnyInBundle) const {
  911.     return hasProperty(MCID::IndirectBranch, Type);
  912.   }
  913.  
  914.   /// Return true if this is a branch which may fall
  915.   /// through to the next instruction or may transfer control flow to some other
  916.   /// block.  The TargetInstrInfo::analyzeBranch method can be used to get more
  917.   /// information about this branch.
  918.   bool isConditionalBranch(QueryType Type = AnyInBundle) const {
  919.     return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
  920.   }
  921.  
  922.   /// Return true if this is a branch which always
  923.   /// transfers control flow to some other block.  The
  924.   /// TargetInstrInfo::analyzeBranch method can be used to get more information
  925.   /// about this branch.
  926.   bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
  927.     return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
  928.   }
  929.  
  930.   /// Return true if this instruction has a predicate operand that
  931.   /// controls execution.  It may be set to 'always', or may be set to other
  932.   /// values.   There are various methods in TargetInstrInfo that can be used to
  933.   /// control and modify the predicate in this instruction.
  934.   bool isPredicable(QueryType Type = AllInBundle) const {
  935.     // If it's a bundle than all bundled instructions must be predicable for this
  936.     // to return true.
  937.     return hasProperty(MCID::Predicable, Type);
  938.   }
  939.  
  940.   /// Return true if this instruction is a comparison.
  941.   bool isCompare(QueryType Type = IgnoreBundle) const {
  942.     return hasProperty(MCID::Compare, Type);
  943.   }
  944.  
  945.   /// Return true if this instruction is a move immediate
  946.   /// (including conditional moves) instruction.
  947.   bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
  948.     return hasProperty(MCID::MoveImm, Type);
  949.   }
  950.  
  951.   /// Return true if this instruction is a register move.
  952.   /// (including moving values from subreg to reg)
  953.   bool isMoveReg(QueryType Type = IgnoreBundle) const {
  954.     return hasProperty(MCID::MoveReg, Type);
  955.   }
  956.  
  957.   /// Return true if this instruction is a bitcast instruction.
  958.   bool isBitcast(QueryType Type = IgnoreBundle) const {
  959.     return hasProperty(MCID::Bitcast, Type);
  960.   }
  961.  
  962.   /// Return true if this instruction is a select instruction.
  963.   bool isSelect(QueryType Type = IgnoreBundle) const {
  964.     return hasProperty(MCID::Select, Type);
  965.   }
  966.  
  967.   /// Return true if this instruction cannot be safely duplicated.
  968.   /// For example, if the instruction has a unique labels attached
  969.   /// to it, duplicating it would cause multiple definition errors.
  970.   bool isNotDuplicable(QueryType Type = AnyInBundle) const {
  971.     if (getPreInstrSymbol() || getPostInstrSymbol())
  972.       return true;
  973.     return hasProperty(MCID::NotDuplicable, Type);
  974.   }
  975.  
  976.   /// Return true if this instruction is convergent.
  977.   /// Convergent instructions can not be made control-dependent on any
  978.   /// additional values.
  979.   bool isConvergent(QueryType Type = AnyInBundle) const {
  980.     if (isInlineAsm()) {
  981.       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
  982.       if (ExtraInfo & InlineAsm::Extra_IsConvergent)
  983.         return true;
  984.     }
  985.     return hasProperty(MCID::Convergent, Type);
  986.   }
  987.  
  988.   /// Returns true if the specified instruction has a delay slot
  989.   /// which must be filled by the code generator.
  990.   bool hasDelaySlot(QueryType Type = AnyInBundle) const {
  991.     return hasProperty(MCID::DelaySlot, Type);
  992.   }
  993.  
  994.   /// Return true for instructions that can be folded as
  995.   /// memory operands in other instructions. The most common use for this
  996.   /// is instructions that are simple loads from memory that don't modify
  997.   /// the loaded value in any way, but it can also be used for instructions
  998.   /// that can be expressed as constant-pool loads, such as V_SETALLONES
  999.   /// on x86, to allow them to be folded when it is beneficial.
  1000.   /// This should only be set on instructions that return a value in their
  1001.   /// only virtual register definition.
  1002.   bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
  1003.     return hasProperty(MCID::FoldableAsLoad, Type);
  1004.   }
  1005.  
  1006.   /// Return true if this instruction behaves
  1007.   /// the same way as the generic REG_SEQUENCE instructions.
  1008.   /// E.g., on ARM,
  1009.   /// dX VMOVDRR rY, rZ
  1010.   /// is equivalent to
  1011.   /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
  1012.   ///
  1013.   /// Note that for the optimizers to be able to take advantage of
  1014.   /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
  1015.   /// override accordingly.
  1016.   bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
  1017.     return hasProperty(MCID::RegSequence, Type);
  1018.   }
  1019.  
  1020.   /// Return true if this instruction behaves
  1021.   /// the same way as the generic EXTRACT_SUBREG instructions.
  1022.   /// E.g., on ARM,
  1023.   /// rX, rY VMOVRRD dZ
  1024.   /// is equivalent to two EXTRACT_SUBREG:
  1025.   /// rX = EXTRACT_SUBREG dZ, ssub_0
  1026.   /// rY = EXTRACT_SUBREG dZ, ssub_1
  1027.   ///
  1028.   /// Note that for the optimizers to be able to take advantage of
  1029.   /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
  1030.   /// override accordingly.
  1031.   bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
  1032.     return hasProperty(MCID::ExtractSubreg, Type);
  1033.   }
  1034.  
  1035.   /// Return true if this instruction behaves
  1036.   /// the same way as the generic INSERT_SUBREG instructions.
  1037.   /// E.g., on ARM,
  1038.   /// dX = VSETLNi32 dY, rZ, Imm
  1039.   /// is equivalent to a INSERT_SUBREG:
  1040.   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
  1041.   ///
  1042.   /// Note that for the optimizers to be able to take advantage of
  1043.   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
  1044.   /// override accordingly.
  1045.   bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
  1046.     return hasProperty(MCID::InsertSubreg, Type);
  1047.   }
  1048.  
  1049.   //===--------------------------------------------------------------------===//
  1050.   // Side Effect Analysis
  1051.   //===--------------------------------------------------------------------===//
  1052.  
  1053.   /// Return true if this instruction could possibly read memory.
  1054.   /// Instructions with this flag set are not necessarily simple load
  1055.   /// instructions, they may load a value and modify it, for example.
  1056.   bool mayLoad(QueryType Type = AnyInBundle) const {
  1057.     if (isInlineAsm()) {
  1058.       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
  1059.       if (ExtraInfo & InlineAsm::Extra_MayLoad)
  1060.         return true;
  1061.     }
  1062.     return hasProperty(MCID::MayLoad, Type);
  1063.   }
  1064.  
  1065.   /// Return true if this instruction could possibly modify memory.
  1066.   /// Instructions with this flag set are not necessarily simple store
  1067.   /// instructions, they may store a modified value based on their operands, or
  1068.   /// may not actually modify anything, for example.
  1069.   bool mayStore(QueryType Type = AnyInBundle) const {
  1070.     if (isInlineAsm()) {
  1071.       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
  1072.       if (ExtraInfo & InlineAsm::Extra_MayStore)
  1073.         return true;
  1074.     }
  1075.     return hasProperty(MCID::MayStore, Type);
  1076.   }
  1077.  
  1078.   /// Return true if this instruction could possibly read or modify memory.
  1079.   bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
  1080.     return mayLoad(Type) || mayStore(Type);
  1081.   }
  1082.  
  1083.   /// Return true if this instruction could possibly raise a floating-point
  1084.   /// exception.  This is the case if the instruction is a floating-point
  1085.   /// instruction that can in principle raise an exception, as indicated
  1086.   /// by the MCID::MayRaiseFPException property, *and* at the same time,
  1087.   /// the instruction is used in a context where we expect floating-point
  1088.   /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
  1089.   bool mayRaiseFPException() const {
  1090.     return hasProperty(MCID::MayRaiseFPException) &&
  1091.            !getFlag(MachineInstr::MIFlag::NoFPExcept);
  1092.   }
  1093.  
  1094.   //===--------------------------------------------------------------------===//
  1095.   // Flags that indicate whether an instruction can be modified by a method.
  1096.   //===--------------------------------------------------------------------===//
  1097.  
  1098.   /// Return true if this may be a 2- or 3-address
  1099.   /// instruction (of the form "X = op Y, Z, ..."), which produces the same
  1100.   /// result if Y and Z are exchanged.  If this flag is set, then the
  1101.   /// TargetInstrInfo::commuteInstruction method may be used to hack on the
  1102.   /// instruction.
  1103.   ///
  1104.   /// Note that this flag may be set on instructions that are only commutable
  1105.   /// sometimes.  In these cases, the call to commuteInstruction will fail.
  1106.   /// Also note that some instructions require non-trivial modification to
  1107.   /// commute them.
  1108.   bool isCommutable(QueryType Type = IgnoreBundle) const {
  1109.     return hasProperty(MCID::Commutable, Type);
  1110.   }
  1111.  
  1112.   /// Return true if this is a 2-address instruction
  1113.   /// which can be changed into a 3-address instruction if needed.  Doing this
  1114.   /// transformation can be profitable in the register allocator, because it
  1115.   /// means that the instruction can use a 2-address form if possible, but
  1116.   /// degrade into a less efficient form if the source and dest register cannot
  1117.   /// be assigned to the same register.  For example, this allows the x86
  1118.   /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
  1119.   /// is the same speed as the shift but has bigger code size.
  1120.   ///
  1121.   /// If this returns true, then the target must implement the
  1122.   /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
  1123.   /// is allowed to fail if the transformation isn't valid for this specific
  1124.   /// instruction (e.g. shl reg, 4 on x86).
  1125.   ///
  1126.   bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
  1127.     return hasProperty(MCID::ConvertibleTo3Addr, Type);
  1128.   }
  1129.  
  1130.   /// Return true if this instruction requires
  1131.   /// custom insertion support when the DAG scheduler is inserting it into a
  1132.   /// machine basic block.  If this is true for the instruction, it basically
  1133.   /// means that it is a pseudo instruction used at SelectionDAG time that is
  1134.   /// expanded out into magic code by the target when MachineInstrs are formed.
  1135.   ///
  1136.   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
  1137.   /// is used to insert this into the MachineBasicBlock.
  1138.   bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
  1139.     return hasProperty(MCID::UsesCustomInserter, Type);
  1140.   }
  1141.  
  1142.   /// Return true if this instruction requires *adjustment*
  1143.   /// after instruction selection by calling a target hook. For example, this
  1144.   /// can be used to fill in ARM 's' optional operand depending on whether
  1145.   /// the conditional flag register is used.
  1146.   bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
  1147.     return hasProperty(MCID::HasPostISelHook, Type);
  1148.   }
  1149.  
  1150.   /// Returns true if this instruction is a candidate for remat.
  1151.   /// This flag is deprecated, please don't use it anymore.  If this
  1152.   /// flag is set, the isReallyTriviallyReMaterializable() method is called to
  1153.   /// verify the instruction is really rematable.
  1154.   bool isRematerializable(QueryType Type = AllInBundle) const {
  1155.     // It's only possible to re-mat a bundle if all bundled instructions are
  1156.     // re-materializable.
  1157.     return hasProperty(MCID::Rematerializable, Type);
  1158.   }
  1159.  
  1160.   /// Returns true if this instruction has the same cost (or less) than a move
  1161.   /// instruction. This is useful during certain types of optimizations
  1162.   /// (e.g., remat during two-address conversion or machine licm)
  1163.   /// where we would like to remat or hoist the instruction, but not if it costs
  1164.   /// more than moving the instruction into the appropriate register. Note, we
  1165.   /// are not marking copies from and to the same register class with this flag.
  1166.   bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
  1167.     // Only returns true for a bundle if all bundled instructions are cheap.
  1168.     return hasProperty(MCID::CheapAsAMove, Type);
  1169.   }
  1170.  
  1171.   /// Returns true if this instruction source operands
  1172.   /// have special register allocation requirements that are not captured by the
  1173.   /// operand register classes. e.g. ARM::STRD's two source registers must be an
  1174.   /// even / odd pair, ARM::STM registers have to be in ascending order.
  1175.   /// Post-register allocation passes should not attempt to change allocations
  1176.   /// for sources of instructions with this flag.
  1177.   bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
  1178.     return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
  1179.   }
  1180.  
  1181.   /// Returns true if this instruction def operands
  1182.   /// have special register allocation requirements that are not captured by the
  1183.   /// operand register classes. e.g. ARM::LDRD's two def registers must be an
  1184.   /// even / odd pair, ARM::LDM registers have to be in ascending order.
  1185.   /// Post-register allocation passes should not attempt to change allocations
  1186.   /// for definitions of instructions with this flag.
  1187.   bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
  1188.     return hasProperty(MCID::ExtraDefRegAllocReq, Type);
  1189.   }
  1190.  
  1191.   enum MICheckType {
  1192.     CheckDefs,      // Check all operands for equality
  1193.     CheckKillDead,  // Check all operands including kill / dead markers
  1194.     IgnoreDefs,     // Ignore all definitions
  1195.     IgnoreVRegDefs  // Ignore virtual register definitions
  1196.   };
  1197.  
  1198.   /// Return true if this instruction is identical to \p Other.
  1199.   /// Two instructions are identical if they have the same opcode and all their
  1200.   /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
  1201.   /// Note that this means liveness related flags (dead, undef, kill) do not
  1202.   /// affect the notion of identical.
  1203.   bool isIdenticalTo(const MachineInstr &Other,
  1204.                      MICheckType Check = CheckDefs) const;
  1205.  
  1206.   /// Returns true if this instruction is a debug instruction that represents an
  1207.   /// identical debug value to \p Other.
  1208.   /// This function considers these debug instructions equivalent if they have
  1209.   /// identical variables, debug locations, and debug operands, and if the
  1210.   /// DIExpressions combined with the directness flags are equivalent.
  1211.   bool isEquivalentDbgInstr(const MachineInstr &Other) const;
  1212.  
  1213.   /// Unlink 'this' from the containing basic block, and return it without
  1214.   /// deleting it.
  1215.   ///
  1216.   /// This function can not be used on bundled instructions, use
  1217.   /// removeFromBundle() to remove individual instructions from a bundle.
  1218.   MachineInstr *removeFromParent();
  1219.  
  1220.   /// Unlink this instruction from its basic block and return it without
  1221.   /// deleting it.
  1222.   ///
  1223.   /// If the instruction is part of a bundle, the other instructions in the
  1224.   /// bundle remain bundled.
  1225.   MachineInstr *removeFromBundle();
  1226.  
  1227.   /// Unlink 'this' from the containing basic block and delete it.
  1228.   ///
  1229.   /// If this instruction is the header of a bundle, the whole bundle is erased.
  1230.   /// This function can not be used for instructions inside a bundle, use
  1231.   /// eraseFromBundle() to erase individual bundled instructions.
  1232.   void eraseFromParent();
  1233.  
  1234.   /// Unlink 'this' form its basic block and delete it.
  1235.   ///
  1236.   /// If the instruction is part of a bundle, the other instructions in the
  1237.   /// bundle remain bundled.
  1238.   void eraseFromBundle();
  1239.  
  1240.   bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
  1241.   bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
  1242.   bool isAnnotationLabel() const {
  1243.     return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
  1244.   }
  1245.  
  1246.   /// Returns true if the MachineInstr represents a label.
  1247.   bool isLabel() const {
  1248.     return isEHLabel() || isGCLabel() || isAnnotationLabel();
  1249.   }
  1250.  
  1251.   bool isCFIInstruction() const {
  1252.     return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
  1253.   }
  1254.  
  1255.   bool isPseudoProbe() const {
  1256.     return getOpcode() == TargetOpcode::PSEUDO_PROBE;
  1257.   }
  1258.  
  1259.   // True if the instruction represents a position in the function.
  1260.   bool isPosition() const { return isLabel() || isCFIInstruction(); }
  1261.  
  1262.   bool isNonListDebugValue() const {
  1263.     return getOpcode() == TargetOpcode::DBG_VALUE;
  1264.   }
  1265.   bool isDebugValueList() const {
  1266.     return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
  1267.   }
  1268.   bool isDebugValue() const {
  1269.     return isNonListDebugValue() || isDebugValueList();
  1270.   }
  1271.   bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
  1272.   bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
  1273.   bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
  1274.   bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
  1275.   bool isDebugInstr() const {
  1276.     return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
  1277.   }
  1278.   bool isDebugOrPseudoInstr() const {
  1279.     return isDebugInstr() || isPseudoProbe();
  1280.   }
  1281.  
  1282.   bool isDebugOffsetImm() const {
  1283.     return isNonListDebugValue() && getDebugOffset().isImm();
  1284.   }
  1285.  
  1286.   /// A DBG_VALUE is indirect iff the location operand is a register and
  1287.   /// the offset operand is an immediate.
  1288.   bool isIndirectDebugValue() const {
  1289.     return isDebugOffsetImm() && getDebugOperand(0).isReg();
  1290.   }
  1291.  
  1292.   /// A DBG_VALUE is an entry value iff its debug expression contains the
  1293.   /// DW_OP_LLVM_entry_value operation.
  1294.   bool isDebugEntryValue() const;
  1295.  
  1296.   /// Return true if the instruction is a debug value which describes a part of
  1297.   /// a variable as unavailable.
  1298.   bool isUndefDebugValue() const {
  1299.     if (!isDebugValue())
  1300.       return false;
  1301.     // If any $noreg locations are given, this DV is undef.
  1302.     for (const MachineOperand &Op : debug_operands())
  1303.       if (Op.isReg() && !Op.getReg().isValid())
  1304.         return true;
  1305.     return false;
  1306.   }
  1307.  
  1308.   bool isPHI() const {
  1309.     return getOpcode() == TargetOpcode::PHI ||
  1310.            getOpcode() == TargetOpcode::G_PHI;
  1311.   }
  1312.   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
  1313.   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
  1314.   bool isInlineAsm() const {
  1315.     return getOpcode() == TargetOpcode::INLINEASM ||
  1316.            getOpcode() == TargetOpcode::INLINEASM_BR;
  1317.   }
  1318.  
  1319.   /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
  1320.   /// specific, be attached to a generic MachineInstr.
  1321.   bool isMSInlineAsm() const {
  1322.     return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
  1323.   }
  1324.  
  1325.   bool isStackAligningInlineAsm() const;
  1326.   InlineAsm::AsmDialect getInlineAsmDialect() const;
  1327.  
  1328.   bool isInsertSubreg() const {
  1329.     return getOpcode() == TargetOpcode::INSERT_SUBREG;
  1330.   }
  1331.  
  1332.   bool isSubregToReg() const {
  1333.     return getOpcode() == TargetOpcode::SUBREG_TO_REG;
  1334.   }
  1335.  
  1336.   bool isRegSequence() const {
  1337.     return getOpcode() == TargetOpcode::REG_SEQUENCE;
  1338.   }
  1339.  
  1340.   bool isBundle() const {
  1341.     return getOpcode() == TargetOpcode::BUNDLE;
  1342.   }
  1343.  
  1344.   bool isCopy() const {
  1345.     return getOpcode() == TargetOpcode::COPY;
  1346.   }
  1347.  
  1348.   bool isFullCopy() const {
  1349.     return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
  1350.   }
  1351.  
  1352.   bool isExtractSubreg() const {
  1353.     return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
  1354.   }
  1355.  
  1356.   /// Return true if the instruction behaves like a copy.
  1357.   /// This does not include native copy instructions.
  1358.   bool isCopyLike() const {
  1359.     return isCopy() || isSubregToReg();
  1360.   }
  1361.  
  1362.   /// Return true is the instruction is an identity copy.
  1363.   bool isIdentityCopy() const {
  1364.     return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
  1365.       getOperand(0).getSubReg() == getOperand(1).getSubReg();
  1366.   }
  1367.  
  1368.   /// Return true if this is a transient instruction that is either very likely
  1369.   /// to be eliminated during register allocation (such as copy-like
  1370.   /// instructions), or if this instruction doesn't have an execution-time cost.
  1371.   bool isTransient() const {
  1372.     switch (getOpcode()) {
  1373.     default:
  1374.       return isMetaInstruction();
  1375.     // Copy-like instructions are usually eliminated during register allocation.
  1376.     case TargetOpcode::PHI:
  1377.     case TargetOpcode::G_PHI:
  1378.     case TargetOpcode::COPY:
  1379.     case TargetOpcode::INSERT_SUBREG:
  1380.     case TargetOpcode::SUBREG_TO_REG:
  1381.     case TargetOpcode::REG_SEQUENCE:
  1382.       return true;
  1383.     }
  1384.   }
  1385.  
  1386.   /// Return the number of instructions inside the MI bundle, excluding the
  1387.   /// bundle header.
  1388.   ///
  1389.   /// This is the number of instructions that MachineBasicBlock::iterator
  1390.   /// skips, 0 for unbundled instructions.
  1391.   unsigned getBundleSize() const;
  1392.  
  1393.   /// Return true if the MachineInstr reads the specified register.
  1394.   /// If TargetRegisterInfo is passed, then it also checks if there
  1395.   /// is a read of a super-register.
  1396.   /// This does not count partial redefines of virtual registers as reads:
  1397.   ///   %reg1024:6 = OP.
  1398.   bool readsRegister(Register Reg,
  1399.                      const TargetRegisterInfo *TRI = nullptr) const {
  1400.     return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
  1401.   }
  1402.  
  1403.   /// Return true if the MachineInstr reads the specified virtual register.
  1404.   /// Take into account that a partial define is a
  1405.   /// read-modify-write operation.
  1406.   bool readsVirtualRegister(Register Reg) const {
  1407.     return readsWritesVirtualRegister(Reg).first;
  1408.   }
  1409.  
  1410.   /// Return a pair of bools (reads, writes) indicating if this instruction
  1411.   /// reads or writes Reg. This also considers partial defines.
  1412.   /// If Ops is not null, all operand indices for Reg are added.
  1413.   std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
  1414.                                 SmallVectorImpl<unsigned> *Ops = nullptr) const;
  1415.  
  1416.   /// Return true if the MachineInstr kills the specified register.
  1417.   /// If TargetRegisterInfo is passed, then it also checks if there is
  1418.   /// a kill of a super-register.
  1419.   bool killsRegister(Register Reg,
  1420.                      const TargetRegisterInfo *TRI = nullptr) const {
  1421.     return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
  1422.   }
  1423.  
  1424.   /// Return true if the MachineInstr fully defines the specified register.
  1425.   /// If TargetRegisterInfo is passed, then it also checks
  1426.   /// if there is a def of a super-register.
  1427.   /// NOTE: It's ignoring subreg indices on virtual registers.
  1428.   bool definesRegister(Register Reg,
  1429.                        const TargetRegisterInfo *TRI = nullptr) const {
  1430.     return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
  1431.   }
  1432.  
  1433.   /// Return true if the MachineInstr modifies (fully define or partially
  1434.   /// define) the specified register.
  1435.   /// NOTE: It's ignoring subreg indices on virtual registers.
  1436.   bool modifiesRegister(Register Reg,
  1437.                         const TargetRegisterInfo *TRI = nullptr) const {
  1438.     return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
  1439.   }
  1440.  
  1441.   /// Returns true if the register is dead in this machine instruction.
  1442.   /// If TargetRegisterInfo is passed, then it also checks
  1443.   /// if there is a dead def of a super-register.
  1444.   bool registerDefIsDead(Register Reg,
  1445.                          const TargetRegisterInfo *TRI = nullptr) const {
  1446.     return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
  1447.   }
  1448.  
  1449.   /// Returns true if the MachineInstr has an implicit-use operand of exactly
  1450.   /// the given register (not considering sub/super-registers).
  1451.   bool hasRegisterImplicitUseOperand(Register Reg) const;
  1452.  
  1453.   /// Returns the operand index that is a use of the specific register or -1
  1454.   /// if it is not found. It further tightens the search criteria to a use
  1455.   /// that kills the register if isKill is true.
  1456.   int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
  1457.                                 const TargetRegisterInfo *TRI = nullptr) const;
  1458.  
  1459.   /// Wrapper for findRegisterUseOperandIdx, it returns
  1460.   /// a pointer to the MachineOperand rather than an index.
  1461.   MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
  1462.                                       const TargetRegisterInfo *TRI = nullptr) {
  1463.     int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
  1464.     return (Idx == -1) ? nullptr : &getOperand(Idx);
  1465.   }
  1466.  
  1467.   const MachineOperand *findRegisterUseOperand(
  1468.     Register Reg, bool isKill = false,
  1469.     const TargetRegisterInfo *TRI = nullptr) const {
  1470.     return const_cast<MachineInstr *>(this)->
  1471.       findRegisterUseOperand(Reg, isKill, TRI);
  1472.   }
  1473.  
  1474.   /// Returns the operand index that is a def of the specified register or
  1475.   /// -1 if it is not found. If isDead is true, defs that are not dead are
  1476.   /// skipped. If Overlap is true, then it also looks for defs that merely
  1477.   /// overlap the specified register. If TargetRegisterInfo is non-null,
  1478.   /// then it also checks if there is a def of a super-register.
  1479.   /// This may also return a register mask operand when Overlap is true.
  1480.   int findRegisterDefOperandIdx(Register Reg,
  1481.                                 bool isDead = false, bool Overlap = false,
  1482.                                 const TargetRegisterInfo *TRI = nullptr) const;
  1483.  
  1484.   /// Wrapper for findRegisterDefOperandIdx, it returns
  1485.   /// a pointer to the MachineOperand rather than an index.
  1486.   MachineOperand *
  1487.   findRegisterDefOperand(Register Reg, bool isDead = false,
  1488.                          bool Overlap = false,
  1489.                          const TargetRegisterInfo *TRI = nullptr) {
  1490.     int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
  1491.     return (Idx == -1) ? nullptr : &getOperand(Idx);
  1492.   }
  1493.  
  1494.   const MachineOperand *
  1495.   findRegisterDefOperand(Register Reg, bool isDead = false,
  1496.                          bool Overlap = false,
  1497.                          const TargetRegisterInfo *TRI = nullptr) const {
  1498.     return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
  1499.         Reg, isDead, Overlap, TRI);
  1500.   }
  1501.  
  1502.   /// Find the index of the first operand in the
  1503.   /// operand list that is used to represent the predicate. It returns -1 if
  1504.   /// none is found.
  1505.   int findFirstPredOperandIdx() const;
  1506.  
  1507.   /// Find the index of the flag word operand that
  1508.   /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
  1509.   /// getOperand(OpIdx) does not belong to an inline asm operand group.
  1510.   ///
  1511.   /// If GroupNo is not NULL, it will receive the number of the operand group
  1512.   /// containing OpIdx.
  1513.   int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
  1514.  
  1515.   /// Compute the static register class constraint for operand OpIdx.
  1516.   /// For normal instructions, this is derived from the MCInstrDesc.
  1517.   /// For inline assembly it is derived from the flag words.
  1518.   ///
  1519.   /// Returns NULL if the static register class constraint cannot be
  1520.   /// determined.
  1521.   const TargetRegisterClass*
  1522.   getRegClassConstraint(unsigned OpIdx,
  1523.                         const TargetInstrInfo *TII,
  1524.                         const TargetRegisterInfo *TRI) const;
  1525.  
  1526.   /// Applies the constraints (def/use) implied by this MI on \p Reg to
  1527.   /// the given \p CurRC.
  1528.   /// If \p ExploreBundle is set and MI is part of a bundle, all the
  1529.   /// instructions inside the bundle will be taken into account. In other words,
  1530.   /// this method accumulates all the constraints of the operand of this MI and
  1531.   /// the related bundle if MI is a bundle or inside a bundle.
  1532.   ///
  1533.   /// Returns the register class that satisfies both \p CurRC and the
  1534.   /// constraints set by MI. Returns NULL if such a register class does not
  1535.   /// exist.
  1536.   ///
  1537.   /// \pre CurRC must not be NULL.
  1538.   const TargetRegisterClass *getRegClassConstraintEffectForVReg(
  1539.       Register Reg, const TargetRegisterClass *CurRC,
  1540.       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
  1541.       bool ExploreBundle = false) const;
  1542.  
  1543.   /// Applies the constraints (def/use) implied by the \p OpIdx operand
  1544.   /// to the given \p CurRC.
  1545.   ///
  1546.   /// Returns the register class that satisfies both \p CurRC and the
  1547.   /// constraints set by \p OpIdx MI. Returns NULL if such a register class
  1548.   /// does not exist.
  1549.   ///
  1550.   /// \pre CurRC must not be NULL.
  1551.   /// \pre The operand at \p OpIdx must be a register.
  1552.   const TargetRegisterClass *
  1553.   getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
  1554.                               const TargetInstrInfo *TII,
  1555.                               const TargetRegisterInfo *TRI) const;
  1556.  
  1557.   /// Add a tie between the register operands at DefIdx and UseIdx.
  1558.   /// The tie will cause the register allocator to ensure that the two
  1559.   /// operands are assigned the same physical register.
  1560.   ///
  1561.   /// Tied operands are managed automatically for explicit operands in the
  1562.   /// MCInstrDesc. This method is for exceptional cases like inline asm.
  1563.   void tieOperands(unsigned DefIdx, unsigned UseIdx);
  1564.  
  1565.   /// Given the index of a tied register operand, find the
  1566.   /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
  1567.   /// index of the tied operand which must exist.
  1568.   unsigned findTiedOperandIdx(unsigned OpIdx) const;
  1569.  
  1570.   /// Given the index of a register def operand,
  1571.   /// check if the register def is tied to a source operand, due to either
  1572.   /// two-address elimination or inline assembly constraints. Returns the
  1573.   /// first tied use operand index by reference if UseOpIdx is not null.
  1574.   bool isRegTiedToUseOperand(unsigned DefOpIdx,
  1575.                              unsigned *UseOpIdx = nullptr) const {
  1576.     const MachineOperand &MO = getOperand(DefOpIdx);
  1577.     if (!MO.isReg() || !MO.isDef() || !MO.isTied())
  1578.       return false;
  1579.     if (UseOpIdx)
  1580.       *UseOpIdx = findTiedOperandIdx(DefOpIdx);
  1581.     return true;
  1582.   }
  1583.  
  1584.   /// Return true if the use operand of the specified index is tied to a def
  1585.   /// operand. It also returns the def operand index by reference if DefOpIdx
  1586.   /// is not null.
  1587.   bool isRegTiedToDefOperand(unsigned UseOpIdx,
  1588.                              unsigned *DefOpIdx = nullptr) const {
  1589.     const MachineOperand &MO = getOperand(UseOpIdx);
  1590.     if (!MO.isReg() || !MO.isUse() || !MO.isTied())
  1591.       return false;
  1592.     if (DefOpIdx)
  1593.       *DefOpIdx = findTiedOperandIdx(UseOpIdx);
  1594.     return true;
  1595.   }
  1596.  
  1597.   /// Clears kill flags on all operands.
  1598.   void clearKillInfo();
  1599.  
  1600.   /// Replace all occurrences of FromReg with ToReg:SubIdx,
  1601.   /// properly composing subreg indices where necessary.
  1602.   void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
  1603.                           const TargetRegisterInfo &RegInfo);
  1604.  
  1605.   /// We have determined MI kills a register. Look for the
  1606.   /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
  1607.   /// add a implicit operand if it's not found. Returns true if the operand
  1608.   /// exists / is added.
  1609.   bool addRegisterKilled(Register IncomingReg,
  1610.                          const TargetRegisterInfo *RegInfo,
  1611.                          bool AddIfNotFound = false);
  1612.  
  1613.   /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
  1614.   /// all aliasing registers.
  1615.   void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
  1616.  
  1617.   /// We have determined MI defined a register without a use.
  1618.   /// Look for the operand that defines it and mark it as IsDead. If
  1619.   /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
  1620.   /// true if the operand exists / is added.
  1621.   bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
  1622.                        bool AddIfNotFound = false);
  1623.  
  1624.   /// Clear all dead flags on operands defining register @p Reg.
  1625.   void clearRegisterDeads(Register Reg);
  1626.  
  1627.   /// Mark all subregister defs of register @p Reg with the undef flag.
  1628.   /// This function is used when we determined to have a subregister def in an
  1629.   /// otherwise undefined super register.
  1630.   void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
  1631.  
  1632.   /// We have determined MI defines a register. Make sure there is an operand
  1633.   /// defining Reg.
  1634.   void addRegisterDefined(Register Reg,
  1635.                           const TargetRegisterInfo *RegInfo = nullptr);
  1636.  
  1637.   /// Mark every physreg used by this instruction as
  1638.   /// dead except those in the UsedRegs list.
  1639.   ///
  1640.   /// On instructions with register mask operands, also add implicit-def
  1641.   /// operands for all registers in UsedRegs.
  1642.   void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
  1643.                              const TargetRegisterInfo &TRI);
  1644.  
  1645.   /// Return true if it is safe to move this instruction. If
  1646.   /// SawStore is set to true, it means that there is a store (or call) between
  1647.   /// the instruction's location and its intended destination.
  1648.   bool isSafeToMove(AAResults *AA, bool &SawStore) const;
  1649.  
  1650.   /// Returns true if this instruction's memory access aliases the memory
  1651.   /// access of Other.
  1652.   //
  1653.   /// Assumes any physical registers used to compute addresses
  1654.   /// have the same value for both instructions.  Returns false if neither
  1655.   /// instruction writes to memory.
  1656.   ///
  1657.   /// @param AA Optional alias analysis, used to compare memory operands.
  1658.   /// @param Other MachineInstr to check aliasing against.
  1659.   /// @param UseTBAA Whether to pass TBAA information to alias analysis.
  1660.   bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
  1661.  
  1662.   /// Return true if this instruction may have an ordered
  1663.   /// or volatile memory reference, or if the information describing the memory
  1664.   /// reference is not available. Return false if it is known to have no
  1665.   /// ordered or volatile memory references.
  1666.   bool hasOrderedMemoryRef() const;
  1667.  
  1668.   /// Return true if this load instruction never traps and points to a memory
  1669.   /// location whose value doesn't change during the execution of this function.
  1670.   ///
  1671.   /// Examples include loading a value from the constant pool or from the
  1672.   /// argument area of a function (if it does not change).  If the instruction
  1673.   /// does multiple loads, this returns true only if all of the loads are
  1674.   /// dereferenceable and invariant.
  1675.   bool isDereferenceableInvariantLoad() const;
  1676.  
  1677.   /// If the specified instruction is a PHI that always merges together the
  1678.   /// same virtual register, return the register, otherwise return 0.
  1679.   unsigned isConstantValuePHI() const;
  1680.  
  1681.   /// Return true if this instruction has side effects that are not modeled
  1682.   /// by mayLoad / mayStore, etc.
  1683.   /// For all instructions, the property is encoded in MCInstrDesc::Flags
  1684.   /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
  1685.   /// INLINEASM instruction, in which case the side effect property is encoded
  1686.   /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
  1687.   ///
  1688.   bool hasUnmodeledSideEffects() const;
  1689.  
  1690.   /// Returns true if it is illegal to fold a load across this instruction.
  1691.   bool isLoadFoldBarrier() const;
  1692.  
  1693.   /// Return true if all the defs of this instruction are dead.
  1694.   bool allDefsAreDead() const;
  1695.  
  1696.   /// Return a valid size if the instruction is a spill instruction.
  1697.   std::optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
  1698.  
  1699.   /// Return a valid size if the instruction is a folded spill instruction.
  1700.   std::optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
  1701.  
  1702.   /// Return a valid size if the instruction is a restore instruction.
  1703.   std::optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
  1704.  
  1705.   /// Return a valid size if the instruction is a folded restore instruction.
  1706.   std::optional<unsigned>
  1707.   getFoldedRestoreSize(const TargetInstrInfo *TII) const;
  1708.  
  1709.   /// Copy implicit register operands from specified
  1710.   /// instruction to this instruction.
  1711.   void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
  1712.  
  1713.   /// Debugging support
  1714.   /// @{
  1715.   /// Determine the generic type to be printed (if needed) on uses and defs.
  1716.   LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
  1717.                      const MachineRegisterInfo &MRI) const;
  1718.  
  1719.   /// Return true when an instruction has tied register that can't be determined
  1720.   /// by the instruction's descriptor. This is useful for MIR printing, to
  1721.   /// determine whether we need to print the ties or not.
  1722.   bool hasComplexRegisterTies() const;
  1723.  
  1724.   /// Print this MI to \p OS.
  1725.   /// Don't print information that can be inferred from other instructions if
  1726.   /// \p IsStandalone is false. It is usually true when only a fragment of the
  1727.   /// function is printed.
  1728.   /// Only print the defs and the opcode if \p SkipOpers is true.
  1729.   /// Otherwise, also print operands if \p SkipDebugLoc is true.
  1730.   /// Otherwise, also print the debug loc, with a terminating newline.
  1731.   /// \p TII is used to print the opcode name.  If it's not present, but the
  1732.   /// MI is in a function, the opcode will be printed using the function's TII.
  1733.   void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
  1734.              bool SkipDebugLoc = false, bool AddNewLine = true,
  1735.              const TargetInstrInfo *TII = nullptr) const;
  1736.   void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
  1737.              bool SkipOpers = false, bool SkipDebugLoc = false,
  1738.              bool AddNewLine = true,
  1739.              const TargetInstrInfo *TII = nullptr) const;
  1740.   void dump() const;
  1741.   /// Print on dbgs() the current instruction and the instructions defining its
  1742.   /// operands and so on until we reach \p MaxDepth.
  1743.   void dumpr(const MachineRegisterInfo &MRI,
  1744.              unsigned MaxDepth = UINT_MAX) const;
  1745.   /// @}
  1746.  
  1747.   //===--------------------------------------------------------------------===//
  1748.   // Accessors used to build up machine instructions.
  1749.  
  1750.   /// Add the specified operand to the instruction.  If it is an implicit
  1751.   /// operand, it is added to the end of the operand list.  If it is an
  1752.   /// explicit operand it is added at the end of the explicit operand list
  1753.   /// (before the first implicit operand).
  1754.   ///
  1755.   /// MF must be the machine function that was used to allocate this
  1756.   /// instruction.
  1757.   ///
  1758.   /// MachineInstrBuilder provides a more convenient interface for creating
  1759.   /// instructions and adding operands.
  1760.   void addOperand(MachineFunction &MF, const MachineOperand &Op);
  1761.  
  1762.   /// Add an operand without providing an MF reference. This only works for
  1763.   /// instructions that are inserted in a basic block.
  1764.   ///
  1765.   /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
  1766.   /// preferred.
  1767.   void addOperand(const MachineOperand &Op);
  1768.  
  1769.   /// Replace the instruction descriptor (thus opcode) of
  1770.   /// the current instruction with a new one.
  1771.   void setDesc(const MCInstrDesc &TID) { MCID = &TID; }
  1772.  
  1773.   /// Replace current source information with new such.
  1774.   /// Avoid using this, the constructor argument is preferable.
  1775.   void setDebugLoc(DebugLoc DL) {
  1776.     DbgLoc = std::move(DL);
  1777.     assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
  1778.   }
  1779.  
  1780.   /// Erase an operand from an instruction, leaving it with one
  1781.   /// fewer operand than it started with.
  1782.   void removeOperand(unsigned OpNo);
  1783.  
  1784.   /// Clear this MachineInstr's memory reference descriptor list.  This resets
  1785.   /// the memrefs to their most conservative state.  This should be used only
  1786.   /// as a last resort since it greatly pessimizes our knowledge of the memory
  1787.   /// access performed by the instruction.
  1788.   void dropMemRefs(MachineFunction &MF);
  1789.  
  1790.   /// Assign this MachineInstr's memory reference descriptor list.
  1791.   ///
  1792.   /// Unlike other methods, this *will* allocate them into a new array
  1793.   /// associated with the provided `MachineFunction`.
  1794.   void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
  1795.  
  1796.   /// Add a MachineMemOperand to the machine instruction.
  1797.   /// This function should be used only occasionally. The setMemRefs function
  1798.   /// is the primary method for setting up a MachineInstr's MemRefs list.
  1799.   void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
  1800.  
  1801.   /// Clone another MachineInstr's memory reference descriptor list and replace
  1802.   /// ours with it.
  1803.   ///
  1804.   /// Note that `*this` may be the incoming MI!
  1805.   ///
  1806.   /// Prefer this API whenever possible as it can avoid allocations in common
  1807.   /// cases.
  1808.   void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
  1809.  
  1810.   /// Clone the merge of multiple MachineInstrs' memory reference descriptors
  1811.   /// list and replace ours with it.
  1812.   ///
  1813.   /// Note that `*this` may be one of the incoming MIs!
  1814.   ///
  1815.   /// Prefer this API whenever possible as it can avoid allocations in common
  1816.   /// cases.
  1817.   void cloneMergedMemRefs(MachineFunction &MF,
  1818.                           ArrayRef<const MachineInstr *> MIs);
  1819.  
  1820.   /// Set a symbol that will be emitted just prior to the instruction itself.
  1821.   ///
  1822.   /// Setting this to a null pointer will remove any such symbol.
  1823.   ///
  1824.   /// FIXME: This is not fully implemented yet.
  1825.   void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
  1826.  
  1827.   /// Set a symbol that will be emitted just after the instruction itself.
  1828.   ///
  1829.   /// Setting this to a null pointer will remove any such symbol.
  1830.   ///
  1831.   /// FIXME: This is not fully implemented yet.
  1832.   void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
  1833.  
  1834.   /// Clone another MachineInstr's pre- and post- instruction symbols and
  1835.   /// replace ours with it.
  1836.   void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
  1837.  
  1838.   /// Set a marker on instructions that denotes where we should create and emit
  1839.   /// heap alloc site labels. This waits until after instruction selection and
  1840.   /// optimizations to create the label, so it should still work if the
  1841.   /// instruction is removed or duplicated.
  1842.   void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
  1843.  
  1844.   // Set metadata on instructions that say which sections to emit instruction
  1845.   // addresses into.
  1846.   void setPCSections(MachineFunction &MF, MDNode *MD);
  1847.  
  1848.   /// Set the CFI type for the instruction.
  1849.   void setCFIType(MachineFunction &MF, uint32_t Type);
  1850.  
  1851.   /// Return the MIFlags which represent both MachineInstrs. This
  1852.   /// should be used when merging two MachineInstrs into one. This routine does
  1853.   /// not modify the MIFlags of this MachineInstr.
  1854.   uint16_t mergeFlagsWith(const MachineInstr& Other) const;
  1855.  
  1856.   static uint16_t copyFlagsFromInstruction(const Instruction &I);
  1857.  
  1858.   /// Copy all flags to MachineInst MIFlags
  1859.   void copyIRFlags(const Instruction &I);
  1860.  
  1861.   /// Break any tie involving OpIdx.
  1862.   void untieRegOperand(unsigned OpIdx) {
  1863.     MachineOperand &MO = getOperand(OpIdx);
  1864.     if (MO.isReg() && MO.isTied()) {
  1865.       getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
  1866.       MO.TiedTo = 0;
  1867.     }
  1868.   }
  1869.  
  1870.   /// Add all implicit def and use operands to this instruction.
  1871.   void addImplicitDefUseOperands(MachineFunction &MF);
  1872.  
  1873.   /// Scan instructions immediately following MI and collect any matching
  1874.   /// DBG_VALUEs.
  1875.   void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
  1876.  
  1877.   /// Find all DBG_VALUEs that point to the register def in this instruction
  1878.   /// and point them to \p Reg instead.
  1879.   void changeDebugValuesDefReg(Register Reg);
  1880.  
  1881.   /// Returns the Intrinsic::ID for this instruction.
  1882.   /// \pre Must have an intrinsic ID operand.
  1883.   unsigned getIntrinsicID() const {
  1884.     return getOperand(getNumExplicitDefs()).getIntrinsicID();
  1885.   }
  1886.  
  1887.   /// Sets all register debug operands in this debug value instruction to be
  1888.   /// undef.
  1889.   void setDebugValueUndef() {
  1890.     assert(isDebugValue() && "Must be a debug value instruction.");
  1891.     for (MachineOperand &MO : debug_operands()) {
  1892.       if (MO.isReg()) {
  1893.         MO.setReg(0);
  1894.         MO.setSubReg(0);
  1895.       }
  1896.     }
  1897.   }
  1898.  
  1899. private:
  1900.   /// If this instruction is embedded into a MachineFunction, return the
  1901.   /// MachineRegisterInfo object for the current function, otherwise
  1902.   /// return null.
  1903.   MachineRegisterInfo *getRegInfo();
  1904.  
  1905.   /// Unlink all of the register operands in this instruction from their
  1906.   /// respective use lists.  This requires that the operands already be on their
  1907.   /// use lists.
  1908.   void removeRegOperandsFromUseLists(MachineRegisterInfo&);
  1909.  
  1910.   /// Add all of the register operands in this instruction from their
  1911.   /// respective use lists.  This requires that the operands not be on their
  1912.   /// use lists yet.
  1913.   void addRegOperandsToUseLists(MachineRegisterInfo&);
  1914.  
  1915.   /// Slow path for hasProperty when we're dealing with a bundle.
  1916.   bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
  1917.  
  1918.   /// Implements the logic of getRegClassConstraintEffectForVReg for the
  1919.   /// this MI and the given operand index \p OpIdx.
  1920.   /// If the related operand does not constrained Reg, this returns CurRC.
  1921.   const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
  1922.       unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
  1923.       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
  1924.  
  1925.   /// Stores extra instruction information inline or allocates as ExtraInfo
  1926.   /// based on the number of pointers.
  1927.   void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
  1928.                     MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
  1929.                     MDNode *HeapAllocMarker, MDNode *PCSections,
  1930.                     uint32_t CFIType);
  1931. };
  1932.  
  1933. /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
  1934. /// instruction rather than by pointer value.
  1935. /// The hashing and equality testing functions ignore definitions so this is
  1936. /// useful for CSE, etc.
  1937. struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
  1938.   static inline MachineInstr *getEmptyKey() {
  1939.     return nullptr;
  1940.   }
  1941.  
  1942.   static inline MachineInstr *getTombstoneKey() {
  1943.     return reinterpret_cast<MachineInstr*>(-1);
  1944.   }
  1945.  
  1946.   static unsigned getHashValue(const MachineInstr* const &MI);
  1947.  
  1948.   static bool isEqual(const MachineInstr* const &LHS,
  1949.                       const MachineInstr* const &RHS) {
  1950.     if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
  1951.         LHS == getEmptyKey() || LHS == getTombstoneKey())
  1952.       return LHS == RHS;
  1953.     return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
  1954.   }
  1955. };
  1956.  
  1957. //===----------------------------------------------------------------------===//
  1958. // Debugging Support
  1959.  
  1960. inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
  1961.   MI.print(OS);
  1962.   return OS;
  1963. }
  1964.  
  1965. } // end namespace llvm
  1966.  
  1967. #endif // LLVM_CODEGEN_MACHINEINSTR_H
  1968.