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  1. //===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This implements routines for translating functions from LLVM IR into
  10. // Machine IR.
  11. //
  12. //===----------------------------------------------------------------------===//
  13.  
  14. #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
  15. #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
  16.  
  17. #include "llvm/ADT/BitVector.h"
  18. #include "llvm/ADT/DenseMap.h"
  19. #include "llvm/ADT/IndexedMap.h"
  20. #include "llvm/ADT/SmallPtrSet.h"
  21. #include "llvm/ADT/SmallVector.h"
  22. #include "llvm/CodeGen/ISDOpcodes.h"
  23. #include "llvm/CodeGen/MachineBasicBlock.h"
  24. #include "llvm/CodeGen/TargetRegisterInfo.h"
  25. #include "llvm/IR/Instructions.h"
  26. #include "llvm/IR/Type.h"
  27. #include "llvm/IR/Value.h"
  28. #include "llvm/Support/KnownBits.h"
  29. #include <cassert>
  30. #include <utility>
  31. #include <vector>
  32.  
  33. namespace llvm {
  34.  
  35. class Argument;
  36. class BasicBlock;
  37. class BranchProbabilityInfo;
  38. class LegacyDivergenceAnalysis;
  39. class Function;
  40. class Instruction;
  41. class MachineFunction;
  42. class MachineInstr;
  43. class MachineRegisterInfo;
  44. class MVT;
  45. class SelectionDAG;
  46. class TargetLowering;
  47.  
  48. //===--------------------------------------------------------------------===//
  49. /// FunctionLoweringInfo - This contains information that is global to a
  50. /// function that is used when lowering a region of the function.
  51. ///
  52. class FunctionLoweringInfo {
  53. public:
  54.   const Function *Fn;
  55.   MachineFunction *MF;
  56.   const TargetLowering *TLI;
  57.   MachineRegisterInfo *RegInfo;
  58.   BranchProbabilityInfo *BPI;
  59.   const LegacyDivergenceAnalysis *DA;
  60.   /// CanLowerReturn - true iff the function's return value can be lowered to
  61.   /// registers.
  62.   bool CanLowerReturn;
  63.  
  64.   /// True if part of the CSRs will be handled via explicit copies.
  65.   bool SplitCSR;
  66.  
  67.   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
  68.   /// allocated to hold a pointer to the hidden sret parameter.
  69.   Register DemoteRegister;
  70.  
  71.   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
  72.   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
  73.  
  74.   /// ValueMap - Since we emit code for the function a basic block at a time,
  75.   /// we must remember which virtual registers hold the values for
  76.   /// cross-basic-block values.
  77.   DenseMap<const Value *, Register> ValueMap;
  78.  
  79.   /// VirtReg2Value map is needed by the Divergence Analysis driven
  80.   /// instruction selection. It is reverted ValueMap. It is computed
  81.   /// in lazy style - on demand. It is used to get the Value corresponding
  82.   /// to the live in virtual register and is called from the
  83.   /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
  84.   DenseMap<Register, const Value*> VirtReg2Value;
  85.  
  86.   /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
  87.   /// to get the Value corresponding to the live-in virtual register.
  88.   const Value *getValueFromVirtualReg(Register Vreg);
  89.  
  90.   /// Track virtual registers created for exception pointers.
  91.   DenseMap<const Value *, Register> CatchPadExceptionPointers;
  92.  
  93.   /// Helper object to track which of three possible relocation mechanisms are
  94.   /// used for a particular value being relocated over a statepoint.
  95.   struct StatepointRelocationRecord {
  96.     enum RelocType {
  97.       // Value did not need to be relocated and can be used directly.
  98.       NoRelocate,
  99.       // Value was spilled to stack and needs filled at the gc.relocate.
  100.       Spill,
  101.       // Value was lowered to tied def and gc.relocate should be replaced with
  102.       // copy from vreg.
  103.       VReg,
  104.       // Value was lowered to tied def and gc.relocate should be replaced with
  105.       // SDValue kept in StatepointLoweringInfo structure. This valid for local
  106.       // relocates only.
  107.       SDValueNode,
  108.     } type = NoRelocate;
  109.     // Payload contains either frame index of the stack slot in which the value
  110.     // was spilled, or virtual register which contains the re-definition.
  111.     union payload_t {
  112.       payload_t() : FI(-1) {}
  113.       int FI;
  114.       Register Reg;
  115.     } payload;
  116.   };
  117.  
  118.   /// Keep track of each value which was relocated and the strategy used to
  119.   /// relocate that value.  This information is required when visiting
  120.   /// gc.relocates which may appear in following blocks.
  121.   using StatepointSpillMapTy =
  122.     DenseMap<const Value *, StatepointRelocationRecord>;
  123.   DenseMap<const Instruction *, StatepointSpillMapTy> StatepointRelocationMaps;
  124.  
  125.   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
  126.   /// the entry block.  This allows the allocas to be efficiently referenced
  127.   /// anywhere in the function.
  128.   DenseMap<const AllocaInst*, int> StaticAllocaMap;
  129.  
  130.   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
  131.   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
  132.  
  133.   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
  134.   /// function arguments that are inserted after scheduling is completed.
  135.   SmallVector<MachineInstr*, 8> ArgDbgValues;
  136.  
  137.   /// Bitvector with a bit set if corresponding argument is described in
  138.   /// ArgDbgValues. Using arg numbers according to Argument numbering.
  139.   BitVector DescribedArgs;
  140.  
  141.   /// RegFixups - Registers which need to be replaced after isel is done.
  142.   DenseMap<Register, Register> RegFixups;
  143.  
  144.   DenseSet<Register> RegsWithFixups;
  145.  
  146.   /// StatepointStackSlots - A list of temporary stack slots (frame indices)
  147.   /// used to spill values at a statepoint.  We store them here to enable
  148.   /// reuse of the same stack slots across different statepoints in different
  149.   /// basic blocks.
  150.   SmallVector<unsigned, 50> StatepointStackSlots;
  151.  
  152.   /// MBB - The current block.
  153.   MachineBasicBlock *MBB;
  154.  
  155.   /// MBB - The current insert position inside the current block.
  156.   MachineBasicBlock::iterator InsertPt;
  157.  
  158.   struct LiveOutInfo {
  159.     unsigned NumSignBits : 31;
  160.     unsigned IsValid : 1;
  161.     KnownBits Known = 1;
  162.  
  163.     LiveOutInfo() : NumSignBits(0), IsValid(true) {}
  164.   };
  165.  
  166.   /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
  167.   /// for a value.
  168.   DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
  169.  
  170.   /// VisitedBBs - The set of basic blocks visited thus far by instruction
  171.   /// selection.
  172.   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
  173.  
  174.   /// PHINodesToUpdate - A list of phi instructions whose operand list will
  175.   /// be updated after processing the current basic block.
  176.   /// TODO: This isn't per-function state, it's per-basic-block state. But
  177.   /// there's no other convenient place for it to live right now.
  178.   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
  179.   unsigned OrigNumPHINodesToUpdate;
  180.  
  181.   /// If the current MBB is a landing pad, the exception pointer and exception
  182.   /// selector registers are copied into these virtual registers by
  183.   /// SelectionDAGISel::PrepareEHLandingPad().
  184.   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
  185.  
  186.   /// set - Initialize this FunctionLoweringInfo with the given Function
  187.   /// and its associated MachineFunction.
  188.   ///
  189.   void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
  190.  
  191.   /// clear - Clear out all the function-specific state. This returns this
  192.   /// FunctionLoweringInfo to an empty state, ready to be used for a
  193.   /// different function.
  194.   void clear();
  195.  
  196.   /// isExportedInst - Return true if the specified value is an instruction
  197.   /// exported from its block.
  198.   bool isExportedInst(const Value *V) const {
  199.     return ValueMap.count(V);
  200.   }
  201.  
  202.   Register CreateReg(MVT VT, bool isDivergent = false);
  203.  
  204.   Register CreateRegs(const Value *V);
  205.  
  206.   Register CreateRegs(Type *Ty, bool isDivergent = false);
  207.  
  208.   Register InitializeRegForValue(const Value *V) {
  209.     // Tokens never live in vregs.
  210.     if (V->getType()->isTokenTy())
  211.       return 0;
  212.     Register &R = ValueMap[V];
  213.     assert(R == 0 && "Already initialized this value register!");
  214.     assert(VirtReg2Value.empty());
  215.     return R = CreateRegs(V);
  216.   }
  217.  
  218.   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
  219.   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
  220.   const LiveOutInfo *GetLiveOutRegInfo(Register Reg) {
  221.     if (!LiveOutRegInfo.inBounds(Reg))
  222.       return nullptr;
  223.  
  224.     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
  225.     if (!LOI->IsValid)
  226.       return nullptr;
  227.  
  228.     return LOI;
  229.   }
  230.  
  231.   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
  232.   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
  233.   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
  234.   /// the larger bit width by zero extension. The bit width must be no smaller
  235.   /// than the LiveOutInfo's existing bit width.
  236.   const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
  237.  
  238.   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
  239.   void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
  240.                          const KnownBits &Known) {
  241.     // Only install this information if it tells us something.
  242.     if (NumSignBits == 1 && Known.isUnknown())
  243.       return;
  244.  
  245.     LiveOutRegInfo.grow(Reg);
  246.     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
  247.     LOI.NumSignBits = NumSignBits;
  248.     LOI.Known.One = Known.One;
  249.     LOI.Known.Zero = Known.Zero;
  250.   }
  251.  
  252.   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
  253.   /// register based on the LiveOutInfo of its operands.
  254.   void ComputePHILiveOutRegInfo(const PHINode*);
  255.  
  256.   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
  257.   /// called when a block is visited before all of its predecessors.
  258.   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
  259.     // PHIs with no uses have no ValueMap entry.
  260.     DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(PN);
  261.     if (It == ValueMap.end())
  262.       return;
  263.  
  264.     Register Reg = It->second;
  265.     if (Reg == 0)
  266.       return;
  267.  
  268.     LiveOutRegInfo.grow(Reg);
  269.     LiveOutRegInfo[Reg].IsValid = false;
  270.   }
  271.  
  272.   /// setArgumentFrameIndex - Record frame index for the byval
  273.   /// argument.
  274.   void setArgumentFrameIndex(const Argument *A, int FI);
  275.  
  276.   /// getArgumentFrameIndex - Get frame index for the byval argument.
  277.   int getArgumentFrameIndex(const Argument *A);
  278.  
  279.   Register getCatchPadExceptionPointerVReg(const Value *CPI,
  280.                                            const TargetRegisterClass *RC);
  281.  
  282. private:
  283.   /// LiveOutRegInfo - Information about live out vregs.
  284.   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
  285. };
  286.  
  287. } // end namespace llvm
  288.  
  289. #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
  290.