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  1. //===----------------------------------------------------------------------===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //
  8. // Compatible with libunwind API documented at:
  9. //   http://www.nongnu.org/libunwind/man/libunwind(3).html
  10. //
  11. //===----------------------------------------------------------------------===//
  12.  
  13. #ifndef __LIBUNWIND__
  14. #define __LIBUNWIND__
  15.  
  16. #include <__libunwind_config.h>
  17.  
  18. #include <stdint.h>
  19. #include <stddef.h>
  20.  
  21. #ifdef __APPLE__
  22.   #if __clang__
  23.     #if __has_include(<Availability.h>)
  24.       #include <Availability.h>
  25.     #endif
  26.   #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
  27.     #include <Availability.h>
  28.   #endif
  29.  
  30.   #ifdef __arm__
  31.      #define LIBUNWIND_AVAIL __attribute__((unavailable))
  32.   #elif defined(__OSX_AVAILABLE_STARTING)
  33.     #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
  34.   #else
  35.     #include <AvailabilityMacros.h>
  36.     #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
  37.       #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
  38.     #else
  39.       #define LIBUNWIND_AVAIL __attribute__((unavailable))
  40.     #endif
  41.   #endif
  42. #else
  43.   #define LIBUNWIND_AVAIL
  44. #endif
  45.  
  46. #if defined(_WIN32) && defined(__SEH__)
  47.   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16)))
  48. #else
  49.   #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR
  50. #endif
  51.  
  52. /* error codes */
  53. enum {
  54.   UNW_ESUCCESS      = 0,     /* no error */
  55.   UNW_EUNSPEC       = -6540, /* unspecified (general) error */
  56.   UNW_ENOMEM        = -6541, /* out of memory */
  57.   UNW_EBADREG       = -6542, /* bad register number */
  58.   UNW_EREADONLYREG  = -6543, /* attempt to write read-only register */
  59.   UNW_ESTOPUNWIND   = -6544, /* stop unwinding */
  60.   UNW_EINVALIDIP    = -6545, /* invalid IP */
  61.   UNW_EBADFRAME     = -6546, /* bad frame */
  62.   UNW_EINVAL        = -6547, /* unsupported operation or bad value */
  63.   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
  64.   UNW_ENOINFO       = -6549  /* no unwind info found */
  65. #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
  66.   , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
  67. #endif
  68. };
  69.  
  70. struct unw_context_t {
  71.   uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
  72. };
  73. typedef struct unw_context_t unw_context_t;
  74.  
  75. struct unw_cursor_t {
  76.   uint64_t data[_LIBUNWIND_CURSOR_SIZE];
  77. } LIBUNWIND_CURSOR_ALIGNMENT_ATTR;
  78. typedef struct unw_cursor_t unw_cursor_t;
  79.  
  80. typedef struct unw_addr_space *unw_addr_space_t;
  81.  
  82. typedef int unw_regnum_t;
  83. typedef uintptr_t unw_word_t;
  84. #if defined(__arm__) && !defined(__ARM_DWARF_EH__) && !defined(__SEH__)
  85. typedef uint64_t unw_fpreg_t;
  86. #else
  87. typedef double unw_fpreg_t;
  88. #endif
  89.  
  90. struct unw_proc_info_t {
  91.   unw_word_t  start_ip;         /* start address of function */
  92.   unw_word_t  end_ip;           /* address after end of function */
  93.   unw_word_t  lsda;             /* address of language specific data area, */
  94.                                 /*  or zero if not used */
  95.   unw_word_t  handler;          /* personality routine, or zero if not used */
  96.   unw_word_t  gp;               /* not used */
  97.   unw_word_t  flags;            /* not used */
  98.   uint32_t    format;           /* compact unwind encoding, or zero if none */
  99.   uint32_t    unwind_info_size; /* size of DWARF unwind info, or zero if none */
  100.   unw_word_t  unwind_info;      /* address of DWARF unwind info, or zero */
  101.   unw_word_t  extra;            /* mach_header of mach-o image containing func */
  102. };
  103. typedef struct unw_proc_info_t unw_proc_info_t;
  104.  
  105. #ifdef __cplusplus
  106. extern "C" {
  107. #endif
  108.  
  109. extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
  110. extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
  111. extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
  112. extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
  113. extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
  114. extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
  115. extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t)  LIBUNWIND_AVAIL;
  116. extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
  117.  
  118. #ifdef __arm__
  119. /* Save VFP registers in FSTMX format (instead of FSTMD). */
  120. extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
  121. #endif
  122.  
  123. #ifdef _AIX
  124. extern uintptr_t unw_get_data_rel_base(unw_cursor_t *) LIBUNWIND_AVAIL;
  125. #endif
  126.  
  127. extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
  128. extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
  129. extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
  130. extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
  131. extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
  132. //extern int       unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
  133.  
  134. extern unw_addr_space_t unw_local_addr_space;
  135.  
  136. #ifdef __cplusplus
  137. }
  138. #endif
  139.  
  140. // architecture independent register numbers
  141. enum {
  142.   UNW_REG_IP = -1, // instruction pointer
  143.   UNW_REG_SP = -2, // stack pointer
  144. };
  145.  
  146. // 32-bit x86 registers
  147. enum {
  148.   UNW_X86_EAX = 0,
  149.   UNW_X86_ECX = 1,
  150.   UNW_X86_EDX = 2,
  151.   UNW_X86_EBX = 3,
  152.   UNW_X86_EBP = 4,
  153.   UNW_X86_ESP = 5,
  154.   UNW_X86_ESI = 6,
  155.   UNW_X86_EDI = 7
  156. };
  157.  
  158. // 64-bit x86_64 registers
  159. enum {
  160.   UNW_X86_64_RAX = 0,
  161.   UNW_X86_64_RDX = 1,
  162.   UNW_X86_64_RCX = 2,
  163.   UNW_X86_64_RBX = 3,
  164.   UNW_X86_64_RSI = 4,
  165.   UNW_X86_64_RDI = 5,
  166.   UNW_X86_64_RBP = 6,
  167.   UNW_X86_64_RSP = 7,
  168.   UNW_X86_64_R8  = 8,
  169.   UNW_X86_64_R9  = 9,
  170.   UNW_X86_64_R10 = 10,
  171.   UNW_X86_64_R11 = 11,
  172.   UNW_X86_64_R12 = 12,
  173.   UNW_X86_64_R13 = 13,
  174.   UNW_X86_64_R14 = 14,
  175.   UNW_X86_64_R15 = 15,
  176.   UNW_X86_64_RIP = 16,
  177.   UNW_X86_64_XMM0 = 17,
  178.   UNW_X86_64_XMM1 = 18,
  179.   UNW_X86_64_XMM2 = 19,
  180.   UNW_X86_64_XMM3 = 20,
  181.   UNW_X86_64_XMM4 = 21,
  182.   UNW_X86_64_XMM5 = 22,
  183.   UNW_X86_64_XMM6 = 23,
  184.   UNW_X86_64_XMM7 = 24,
  185.   UNW_X86_64_XMM8 = 25,
  186.   UNW_X86_64_XMM9 = 26,
  187.   UNW_X86_64_XMM10 = 27,
  188.   UNW_X86_64_XMM11 = 28,
  189.   UNW_X86_64_XMM12 = 29,
  190.   UNW_X86_64_XMM13 = 30,
  191.   UNW_X86_64_XMM14 = 31,
  192.   UNW_X86_64_XMM15 = 32,
  193. };
  194.  
  195.  
  196. // 32-bit ppc register numbers
  197. enum {
  198.   UNW_PPC_R0  = 0,
  199.   UNW_PPC_R1  = 1,
  200.   UNW_PPC_R2  = 2,
  201.   UNW_PPC_R3  = 3,
  202.   UNW_PPC_R4  = 4,
  203.   UNW_PPC_R5  = 5,
  204.   UNW_PPC_R6  = 6,
  205.   UNW_PPC_R7  = 7,
  206.   UNW_PPC_R8  = 8,
  207.   UNW_PPC_R9  = 9,
  208.   UNW_PPC_R10 = 10,
  209.   UNW_PPC_R11 = 11,
  210.   UNW_PPC_R12 = 12,
  211.   UNW_PPC_R13 = 13,
  212.   UNW_PPC_R14 = 14,
  213.   UNW_PPC_R15 = 15,
  214.   UNW_PPC_R16 = 16,
  215.   UNW_PPC_R17 = 17,
  216.   UNW_PPC_R18 = 18,
  217.   UNW_PPC_R19 = 19,
  218.   UNW_PPC_R20 = 20,
  219.   UNW_PPC_R21 = 21,
  220.   UNW_PPC_R22 = 22,
  221.   UNW_PPC_R23 = 23,
  222.   UNW_PPC_R24 = 24,
  223.   UNW_PPC_R25 = 25,
  224.   UNW_PPC_R26 = 26,
  225.   UNW_PPC_R27 = 27,
  226.   UNW_PPC_R28 = 28,
  227.   UNW_PPC_R29 = 29,
  228.   UNW_PPC_R30 = 30,
  229.   UNW_PPC_R31 = 31,
  230.   UNW_PPC_F0  = 32,
  231.   UNW_PPC_F1  = 33,
  232.   UNW_PPC_F2  = 34,
  233.   UNW_PPC_F3  = 35,
  234.   UNW_PPC_F4  = 36,
  235.   UNW_PPC_F5  = 37,
  236.   UNW_PPC_F6  = 38,
  237.   UNW_PPC_F7  = 39,
  238.   UNW_PPC_F8  = 40,
  239.   UNW_PPC_F9  = 41,
  240.   UNW_PPC_F10 = 42,
  241.   UNW_PPC_F11 = 43,
  242.   UNW_PPC_F12 = 44,
  243.   UNW_PPC_F13 = 45,
  244.   UNW_PPC_F14 = 46,
  245.   UNW_PPC_F15 = 47,
  246.   UNW_PPC_F16 = 48,
  247.   UNW_PPC_F17 = 49,
  248.   UNW_PPC_F18 = 50,
  249.   UNW_PPC_F19 = 51,
  250.   UNW_PPC_F20 = 52,
  251.   UNW_PPC_F21 = 53,
  252.   UNW_PPC_F22 = 54,
  253.   UNW_PPC_F23 = 55,
  254.   UNW_PPC_F24 = 56,
  255.   UNW_PPC_F25 = 57,
  256.   UNW_PPC_F26 = 58,
  257.   UNW_PPC_F27 = 59,
  258.   UNW_PPC_F28 = 60,
  259.   UNW_PPC_F29 = 61,
  260.   UNW_PPC_F30 = 62,
  261.   UNW_PPC_F31 = 63,
  262.   UNW_PPC_MQ  = 64,
  263.   UNW_PPC_LR  = 65,
  264.   UNW_PPC_CTR = 66,
  265.   UNW_PPC_AP  = 67,
  266.   UNW_PPC_CR0 = 68,
  267.   UNW_PPC_CR1 = 69,
  268.   UNW_PPC_CR2 = 70,
  269.   UNW_PPC_CR3 = 71,
  270.   UNW_PPC_CR4 = 72,
  271.   UNW_PPC_CR5 = 73,
  272.   UNW_PPC_CR6 = 74,
  273.   UNW_PPC_CR7 = 75,
  274.   UNW_PPC_XER = 76,
  275.   UNW_PPC_V0  = 77,
  276.   UNW_PPC_V1  = 78,
  277.   UNW_PPC_V2  = 79,
  278.   UNW_PPC_V3  = 80,
  279.   UNW_PPC_V4  = 81,
  280.   UNW_PPC_V5  = 82,
  281.   UNW_PPC_V6  = 83,
  282.   UNW_PPC_V7  = 84,
  283.   UNW_PPC_V8  = 85,
  284.   UNW_PPC_V9  = 86,
  285.   UNW_PPC_V10 = 87,
  286.   UNW_PPC_V11 = 88,
  287.   UNW_PPC_V12 = 89,
  288.   UNW_PPC_V13 = 90,
  289.   UNW_PPC_V14 = 91,
  290.   UNW_PPC_V15 = 92,
  291.   UNW_PPC_V16 = 93,
  292.   UNW_PPC_V17 = 94,
  293.   UNW_PPC_V18 = 95,
  294.   UNW_PPC_V19 = 96,
  295.   UNW_PPC_V20 = 97,
  296.   UNW_PPC_V21 = 98,
  297.   UNW_PPC_V22 = 99,
  298.   UNW_PPC_V23 = 100,
  299.   UNW_PPC_V24 = 101,
  300.   UNW_PPC_V25 = 102,
  301.   UNW_PPC_V26 = 103,
  302.   UNW_PPC_V27 = 104,
  303.   UNW_PPC_V28 = 105,
  304.   UNW_PPC_V29 = 106,
  305.   UNW_PPC_V30 = 107,
  306.   UNW_PPC_V31 = 108,
  307.   UNW_PPC_VRSAVE  = 109,
  308.   UNW_PPC_VSCR    = 110,
  309.   UNW_PPC_SPE_ACC = 111,
  310.   UNW_PPC_SPEFSCR = 112
  311. };
  312.  
  313. // 64-bit ppc register numbers
  314. enum {
  315.   UNW_PPC64_R0      = 0,
  316.   UNW_PPC64_R1      = 1,
  317.   UNW_PPC64_R2      = 2,
  318.   UNW_PPC64_R3      = 3,
  319.   UNW_PPC64_R4      = 4,
  320.   UNW_PPC64_R5      = 5,
  321.   UNW_PPC64_R6      = 6,
  322.   UNW_PPC64_R7      = 7,
  323.   UNW_PPC64_R8      = 8,
  324.   UNW_PPC64_R9      = 9,
  325.   UNW_PPC64_R10     = 10,
  326.   UNW_PPC64_R11     = 11,
  327.   UNW_PPC64_R12     = 12,
  328.   UNW_PPC64_R13     = 13,
  329.   UNW_PPC64_R14     = 14,
  330.   UNW_PPC64_R15     = 15,
  331.   UNW_PPC64_R16     = 16,
  332.   UNW_PPC64_R17     = 17,
  333.   UNW_PPC64_R18     = 18,
  334.   UNW_PPC64_R19     = 19,
  335.   UNW_PPC64_R20     = 20,
  336.   UNW_PPC64_R21     = 21,
  337.   UNW_PPC64_R22     = 22,
  338.   UNW_PPC64_R23     = 23,
  339.   UNW_PPC64_R24     = 24,
  340.   UNW_PPC64_R25     = 25,
  341.   UNW_PPC64_R26     = 26,
  342.   UNW_PPC64_R27     = 27,
  343.   UNW_PPC64_R28     = 28,
  344.   UNW_PPC64_R29     = 29,
  345.   UNW_PPC64_R30     = 30,
  346.   UNW_PPC64_R31     = 31,
  347.   UNW_PPC64_F0      = 32,
  348.   UNW_PPC64_F1      = 33,
  349.   UNW_PPC64_F2      = 34,
  350.   UNW_PPC64_F3      = 35,
  351.   UNW_PPC64_F4      = 36,
  352.   UNW_PPC64_F5      = 37,
  353.   UNW_PPC64_F6      = 38,
  354.   UNW_PPC64_F7      = 39,
  355.   UNW_PPC64_F8      = 40,
  356.   UNW_PPC64_F9      = 41,
  357.   UNW_PPC64_F10     = 42,
  358.   UNW_PPC64_F11     = 43,
  359.   UNW_PPC64_F12     = 44,
  360.   UNW_PPC64_F13     = 45,
  361.   UNW_PPC64_F14     = 46,
  362.   UNW_PPC64_F15     = 47,
  363.   UNW_PPC64_F16     = 48,
  364.   UNW_PPC64_F17     = 49,
  365.   UNW_PPC64_F18     = 50,
  366.   UNW_PPC64_F19     = 51,
  367.   UNW_PPC64_F20     = 52,
  368.   UNW_PPC64_F21     = 53,
  369.   UNW_PPC64_F22     = 54,
  370.   UNW_PPC64_F23     = 55,
  371.   UNW_PPC64_F24     = 56,
  372.   UNW_PPC64_F25     = 57,
  373.   UNW_PPC64_F26     = 58,
  374.   UNW_PPC64_F27     = 59,
  375.   UNW_PPC64_F28     = 60,
  376.   UNW_PPC64_F29     = 61,
  377.   UNW_PPC64_F30     = 62,
  378.   UNW_PPC64_F31     = 63,
  379.   // 64: reserved
  380.   UNW_PPC64_LR      = 65,
  381.   UNW_PPC64_CTR     = 66,
  382.   // 67: reserved
  383.   UNW_PPC64_CR0     = 68,
  384.   UNW_PPC64_CR1     = 69,
  385.   UNW_PPC64_CR2     = 70,
  386.   UNW_PPC64_CR3     = 71,
  387.   UNW_PPC64_CR4     = 72,
  388.   UNW_PPC64_CR5     = 73,
  389.   UNW_PPC64_CR6     = 74,
  390.   UNW_PPC64_CR7     = 75,
  391.   UNW_PPC64_XER     = 76,
  392.   UNW_PPC64_V0      = 77,
  393.   UNW_PPC64_V1      = 78,
  394.   UNW_PPC64_V2      = 79,
  395.   UNW_PPC64_V3      = 80,
  396.   UNW_PPC64_V4      = 81,
  397.   UNW_PPC64_V5      = 82,
  398.   UNW_PPC64_V6      = 83,
  399.   UNW_PPC64_V7      = 84,
  400.   UNW_PPC64_V8      = 85,
  401.   UNW_PPC64_V9      = 86,
  402.   UNW_PPC64_V10     = 87,
  403.   UNW_PPC64_V11     = 88,
  404.   UNW_PPC64_V12     = 89,
  405.   UNW_PPC64_V13     = 90,
  406.   UNW_PPC64_V14     = 91,
  407.   UNW_PPC64_V15     = 92,
  408.   UNW_PPC64_V16     = 93,
  409.   UNW_PPC64_V17     = 94,
  410.   UNW_PPC64_V18     = 95,
  411.   UNW_PPC64_V19     = 96,
  412.   UNW_PPC64_V20     = 97,
  413.   UNW_PPC64_V21     = 98,
  414.   UNW_PPC64_V22     = 99,
  415.   UNW_PPC64_V23     = 100,
  416.   UNW_PPC64_V24     = 101,
  417.   UNW_PPC64_V25     = 102,
  418.   UNW_PPC64_V26     = 103,
  419.   UNW_PPC64_V27     = 104,
  420.   UNW_PPC64_V28     = 105,
  421.   UNW_PPC64_V29     = 106,
  422.   UNW_PPC64_V30     = 107,
  423.   UNW_PPC64_V31     = 108,
  424.   // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
  425.   // Borrowing VRSAVE number from PPC32.
  426.   UNW_PPC64_VRSAVE  = 109,
  427.   UNW_PPC64_VSCR    = 110,
  428.   UNW_PPC64_TFHAR   = 114,
  429.   UNW_PPC64_TFIAR   = 115,
  430.   UNW_PPC64_TEXASR  = 116,
  431.   UNW_PPC64_VS0     = UNW_PPC64_F0,
  432.   UNW_PPC64_VS1     = UNW_PPC64_F1,
  433.   UNW_PPC64_VS2     = UNW_PPC64_F2,
  434.   UNW_PPC64_VS3     = UNW_PPC64_F3,
  435.   UNW_PPC64_VS4     = UNW_PPC64_F4,
  436.   UNW_PPC64_VS5     = UNW_PPC64_F5,
  437.   UNW_PPC64_VS6     = UNW_PPC64_F6,
  438.   UNW_PPC64_VS7     = UNW_PPC64_F7,
  439.   UNW_PPC64_VS8     = UNW_PPC64_F8,
  440.   UNW_PPC64_VS9     = UNW_PPC64_F9,
  441.   UNW_PPC64_VS10    = UNW_PPC64_F10,
  442.   UNW_PPC64_VS11    = UNW_PPC64_F11,
  443.   UNW_PPC64_VS12    = UNW_PPC64_F12,
  444.   UNW_PPC64_VS13    = UNW_PPC64_F13,
  445.   UNW_PPC64_VS14    = UNW_PPC64_F14,
  446.   UNW_PPC64_VS15    = UNW_PPC64_F15,
  447.   UNW_PPC64_VS16    = UNW_PPC64_F16,
  448.   UNW_PPC64_VS17    = UNW_PPC64_F17,
  449.   UNW_PPC64_VS18    = UNW_PPC64_F18,
  450.   UNW_PPC64_VS19    = UNW_PPC64_F19,
  451.   UNW_PPC64_VS20    = UNW_PPC64_F20,
  452.   UNW_PPC64_VS21    = UNW_PPC64_F21,
  453.   UNW_PPC64_VS22    = UNW_PPC64_F22,
  454.   UNW_PPC64_VS23    = UNW_PPC64_F23,
  455.   UNW_PPC64_VS24    = UNW_PPC64_F24,
  456.   UNW_PPC64_VS25    = UNW_PPC64_F25,
  457.   UNW_PPC64_VS26    = UNW_PPC64_F26,
  458.   UNW_PPC64_VS27    = UNW_PPC64_F27,
  459.   UNW_PPC64_VS28    = UNW_PPC64_F28,
  460.   UNW_PPC64_VS29    = UNW_PPC64_F29,
  461.   UNW_PPC64_VS30    = UNW_PPC64_F30,
  462.   UNW_PPC64_VS31    = UNW_PPC64_F31,
  463.   UNW_PPC64_VS32    = UNW_PPC64_V0,
  464.   UNW_PPC64_VS33    = UNW_PPC64_V1,
  465.   UNW_PPC64_VS34    = UNW_PPC64_V2,
  466.   UNW_PPC64_VS35    = UNW_PPC64_V3,
  467.   UNW_PPC64_VS36    = UNW_PPC64_V4,
  468.   UNW_PPC64_VS37    = UNW_PPC64_V5,
  469.   UNW_PPC64_VS38    = UNW_PPC64_V6,
  470.   UNW_PPC64_VS39    = UNW_PPC64_V7,
  471.   UNW_PPC64_VS40    = UNW_PPC64_V8,
  472.   UNW_PPC64_VS41    = UNW_PPC64_V9,
  473.   UNW_PPC64_VS42    = UNW_PPC64_V10,
  474.   UNW_PPC64_VS43    = UNW_PPC64_V11,
  475.   UNW_PPC64_VS44    = UNW_PPC64_V12,
  476.   UNW_PPC64_VS45    = UNW_PPC64_V13,
  477.   UNW_PPC64_VS46    = UNW_PPC64_V14,
  478.   UNW_PPC64_VS47    = UNW_PPC64_V15,
  479.   UNW_PPC64_VS48    = UNW_PPC64_V16,
  480.   UNW_PPC64_VS49    = UNW_PPC64_V17,
  481.   UNW_PPC64_VS50    = UNW_PPC64_V18,
  482.   UNW_PPC64_VS51    = UNW_PPC64_V19,
  483.   UNW_PPC64_VS52    = UNW_PPC64_V20,
  484.   UNW_PPC64_VS53    = UNW_PPC64_V21,
  485.   UNW_PPC64_VS54    = UNW_PPC64_V22,
  486.   UNW_PPC64_VS55    = UNW_PPC64_V23,
  487.   UNW_PPC64_VS56    = UNW_PPC64_V24,
  488.   UNW_PPC64_VS57    = UNW_PPC64_V25,
  489.   UNW_PPC64_VS58    = UNW_PPC64_V26,
  490.   UNW_PPC64_VS59    = UNW_PPC64_V27,
  491.   UNW_PPC64_VS60    = UNW_PPC64_V28,
  492.   UNW_PPC64_VS61    = UNW_PPC64_V29,
  493.   UNW_PPC64_VS62    = UNW_PPC64_V30,
  494.   UNW_PPC64_VS63    = UNW_PPC64_V31
  495. };
  496.  
  497. // 64-bit ARM64 registers
  498. enum {
  499.   UNW_AARCH64_X0 = 0,
  500.   UNW_AARCH64_X1 = 1,
  501.   UNW_AARCH64_X2 = 2,
  502.   UNW_AARCH64_X3 = 3,
  503.   UNW_AARCH64_X4 = 4,
  504.   UNW_AARCH64_X5 = 5,
  505.   UNW_AARCH64_X6 = 6,
  506.   UNW_AARCH64_X7 = 7,
  507.   UNW_AARCH64_X8 = 8,
  508.   UNW_AARCH64_X9 = 9,
  509.   UNW_AARCH64_X10 = 10,
  510.   UNW_AARCH64_X11 = 11,
  511.   UNW_AARCH64_X12 = 12,
  512.   UNW_AARCH64_X13 = 13,
  513.   UNW_AARCH64_X14 = 14,
  514.   UNW_AARCH64_X15 = 15,
  515.   UNW_AARCH64_X16 = 16,
  516.   UNW_AARCH64_X17 = 17,
  517.   UNW_AARCH64_X18 = 18,
  518.   UNW_AARCH64_X19 = 19,
  519.   UNW_AARCH64_X20 = 20,
  520.   UNW_AARCH64_X21 = 21,
  521.   UNW_AARCH64_X22 = 22,
  522.   UNW_AARCH64_X23 = 23,
  523.   UNW_AARCH64_X24 = 24,
  524.   UNW_AARCH64_X25 = 25,
  525.   UNW_AARCH64_X26 = 26,
  526.   UNW_AARCH64_X27 = 27,
  527.   UNW_AARCH64_X28 = 28,
  528.   UNW_AARCH64_X29 = 29,
  529.   UNW_AARCH64_FP = 29,
  530.   UNW_AARCH64_X30 = 30,
  531.   UNW_AARCH64_LR = 30,
  532.   UNW_AARCH64_X31 = 31,
  533.   UNW_AARCH64_SP = 31,
  534.   UNW_AARCH64_PC = 32,
  535.  
  536.   // reserved block
  537.   UNW_AARCH64_RA_SIGN_STATE = 34,
  538.  
  539.   // FP/vector registers
  540.   UNW_AARCH64_V0 = 64,
  541.   UNW_AARCH64_V1 = 65,
  542.   UNW_AARCH64_V2 = 66,
  543.   UNW_AARCH64_V3 = 67,
  544.   UNW_AARCH64_V4 = 68,
  545.   UNW_AARCH64_V5 = 69,
  546.   UNW_AARCH64_V6 = 70,
  547.   UNW_AARCH64_V7 = 71,
  548.   UNW_AARCH64_V8 = 72,
  549.   UNW_AARCH64_V9 = 73,
  550.   UNW_AARCH64_V10 = 74,
  551.   UNW_AARCH64_V11 = 75,
  552.   UNW_AARCH64_V12 = 76,
  553.   UNW_AARCH64_V13 = 77,
  554.   UNW_AARCH64_V14 = 78,
  555.   UNW_AARCH64_V15 = 79,
  556.   UNW_AARCH64_V16 = 80,
  557.   UNW_AARCH64_V17 = 81,
  558.   UNW_AARCH64_V18 = 82,
  559.   UNW_AARCH64_V19 = 83,
  560.   UNW_AARCH64_V20 = 84,
  561.   UNW_AARCH64_V21 = 85,
  562.   UNW_AARCH64_V22 = 86,
  563.   UNW_AARCH64_V23 = 87,
  564.   UNW_AARCH64_V24 = 88,
  565.   UNW_AARCH64_V25 = 89,
  566.   UNW_AARCH64_V26 = 90,
  567.   UNW_AARCH64_V27 = 91,
  568.   UNW_AARCH64_V28 = 92,
  569.   UNW_AARCH64_V29 = 93,
  570.   UNW_AARCH64_V30 = 94,
  571.   UNW_AARCH64_V31 = 95,
  572.  
  573.   // Compatibility aliases
  574.   UNW_ARM64_X0 = UNW_AARCH64_X0,
  575.   UNW_ARM64_X1 = UNW_AARCH64_X1,
  576.   UNW_ARM64_X2 = UNW_AARCH64_X2,
  577.   UNW_ARM64_X3 = UNW_AARCH64_X3,
  578.   UNW_ARM64_X4 = UNW_AARCH64_X4,
  579.   UNW_ARM64_X5 = UNW_AARCH64_X5,
  580.   UNW_ARM64_X6 = UNW_AARCH64_X6,
  581.   UNW_ARM64_X7 = UNW_AARCH64_X7,
  582.   UNW_ARM64_X8 = UNW_AARCH64_X8,
  583.   UNW_ARM64_X9 = UNW_AARCH64_X9,
  584.   UNW_ARM64_X10 = UNW_AARCH64_X10,
  585.   UNW_ARM64_X11 = UNW_AARCH64_X11,
  586.   UNW_ARM64_X12 = UNW_AARCH64_X12,
  587.   UNW_ARM64_X13 = UNW_AARCH64_X13,
  588.   UNW_ARM64_X14 = UNW_AARCH64_X14,
  589.   UNW_ARM64_X15 = UNW_AARCH64_X15,
  590.   UNW_ARM64_X16 = UNW_AARCH64_X16,
  591.   UNW_ARM64_X17 = UNW_AARCH64_X17,
  592.   UNW_ARM64_X18 = UNW_AARCH64_X18,
  593.   UNW_ARM64_X19 = UNW_AARCH64_X19,
  594.   UNW_ARM64_X20 = UNW_AARCH64_X20,
  595.   UNW_ARM64_X21 = UNW_AARCH64_X21,
  596.   UNW_ARM64_X22 = UNW_AARCH64_X22,
  597.   UNW_ARM64_X23 = UNW_AARCH64_X23,
  598.   UNW_ARM64_X24 = UNW_AARCH64_X24,
  599.   UNW_ARM64_X25 = UNW_AARCH64_X25,
  600.   UNW_ARM64_X26 = UNW_AARCH64_X26,
  601.   UNW_ARM64_X27 = UNW_AARCH64_X27,
  602.   UNW_ARM64_X28 = UNW_AARCH64_X28,
  603.   UNW_ARM64_X29 = UNW_AARCH64_X29,
  604.   UNW_ARM64_FP = UNW_AARCH64_FP,
  605.   UNW_ARM64_X30 = UNW_AARCH64_X30,
  606.   UNW_ARM64_LR = UNW_AARCH64_LR,
  607.   UNW_ARM64_X31 = UNW_AARCH64_X31,
  608.   UNW_ARM64_SP = UNW_AARCH64_SP,
  609.   UNW_ARM64_PC = UNW_AARCH64_PC,
  610.   UNW_ARM64_RA_SIGN_STATE = UNW_AARCH64_RA_SIGN_STATE,
  611.   UNW_ARM64_D0 = UNW_AARCH64_V0,
  612.   UNW_ARM64_D1 = UNW_AARCH64_V1,
  613.   UNW_ARM64_D2 = UNW_AARCH64_V2,
  614.   UNW_ARM64_D3 = UNW_AARCH64_V3,
  615.   UNW_ARM64_D4 = UNW_AARCH64_V4,
  616.   UNW_ARM64_D5 = UNW_AARCH64_V5,
  617.   UNW_ARM64_D6 = UNW_AARCH64_V6,
  618.   UNW_ARM64_D7 = UNW_AARCH64_V7,
  619.   UNW_ARM64_D8 = UNW_AARCH64_V8,
  620.   UNW_ARM64_D9 = UNW_AARCH64_V9,
  621.   UNW_ARM64_D10 = UNW_AARCH64_V10,
  622.   UNW_ARM64_D11 = UNW_AARCH64_V11,
  623.   UNW_ARM64_D12 = UNW_AARCH64_V12,
  624.   UNW_ARM64_D13 = UNW_AARCH64_V13,
  625.   UNW_ARM64_D14 = UNW_AARCH64_V14,
  626.   UNW_ARM64_D15 = UNW_AARCH64_V15,
  627.   UNW_ARM64_D16 = UNW_AARCH64_V16,
  628.   UNW_ARM64_D17 = UNW_AARCH64_V17,
  629.   UNW_ARM64_D18 = UNW_AARCH64_V18,
  630.   UNW_ARM64_D19 = UNW_AARCH64_V19,
  631.   UNW_ARM64_D20 = UNW_AARCH64_V20,
  632.   UNW_ARM64_D21 = UNW_AARCH64_V21,
  633.   UNW_ARM64_D22 = UNW_AARCH64_V22,
  634.   UNW_ARM64_D23 = UNW_AARCH64_V23,
  635.   UNW_ARM64_D24 = UNW_AARCH64_V24,
  636.   UNW_ARM64_D25 = UNW_AARCH64_V25,
  637.   UNW_ARM64_D26 = UNW_AARCH64_V26,
  638.   UNW_ARM64_D27 = UNW_AARCH64_V27,
  639.   UNW_ARM64_D28 = UNW_AARCH64_V28,
  640.   UNW_ARM64_D29 = UNW_AARCH64_V29,
  641.   UNW_ARM64_D30 = UNW_AARCH64_V30,
  642.   UNW_ARM64_D31 = UNW_AARCH64_V31,
  643. };
  644.  
  645. // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
  646. // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
  647. // In this scheme, even though the 64-bit floating point registers D0-D31
  648. // overlap physically with the 32-bit floating pointer registers S0-S31,
  649. // they are given a non-overlapping range of register numbers.
  650. //
  651. // Commented out ranges are not preserved during unwinding.
  652. enum {
  653.   UNW_ARM_R0  = 0,
  654.   UNW_ARM_R1  = 1,
  655.   UNW_ARM_R2  = 2,
  656.   UNW_ARM_R3  = 3,
  657.   UNW_ARM_R4  = 4,
  658.   UNW_ARM_R5  = 5,
  659.   UNW_ARM_R6  = 6,
  660.   UNW_ARM_R7  = 7,
  661.   UNW_ARM_R8  = 8,
  662.   UNW_ARM_R9  = 9,
  663.   UNW_ARM_R10 = 10,
  664.   UNW_ARM_R11 = 11,
  665.   UNW_ARM_R12 = 12,
  666.   UNW_ARM_SP  = 13,  // Logical alias for UNW_REG_SP
  667.   UNW_ARM_R13 = 13,
  668.   UNW_ARM_LR  = 14,
  669.   UNW_ARM_R14 = 14,
  670.   UNW_ARM_IP  = 15,  // Logical alias for UNW_REG_IP
  671.   UNW_ARM_R15 = 15,
  672.   // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
  673.   UNW_ARM_S0  = 64,
  674.   UNW_ARM_S1  = 65,
  675.   UNW_ARM_S2  = 66,
  676.   UNW_ARM_S3  = 67,
  677.   UNW_ARM_S4  = 68,
  678.   UNW_ARM_S5  = 69,
  679.   UNW_ARM_S6  = 70,
  680.   UNW_ARM_S7  = 71,
  681.   UNW_ARM_S8  = 72,
  682.   UNW_ARM_S9  = 73,
  683.   UNW_ARM_S10 = 74,
  684.   UNW_ARM_S11 = 75,
  685.   UNW_ARM_S12 = 76,
  686.   UNW_ARM_S13 = 77,
  687.   UNW_ARM_S14 = 78,
  688.   UNW_ARM_S15 = 79,
  689.   UNW_ARM_S16 = 80,
  690.   UNW_ARM_S17 = 81,
  691.   UNW_ARM_S18 = 82,
  692.   UNW_ARM_S19 = 83,
  693.   UNW_ARM_S20 = 84,
  694.   UNW_ARM_S21 = 85,
  695.   UNW_ARM_S22 = 86,
  696.   UNW_ARM_S23 = 87,
  697.   UNW_ARM_S24 = 88,
  698.   UNW_ARM_S25 = 89,
  699.   UNW_ARM_S26 = 90,
  700.   UNW_ARM_S27 = 91,
  701.   UNW_ARM_S28 = 92,
  702.   UNW_ARM_S29 = 93,
  703.   UNW_ARM_S30 = 94,
  704.   UNW_ARM_S31 = 95,
  705.   //  96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
  706.   // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
  707.   UNW_ARM_WR0 = 112,
  708.   UNW_ARM_WR1 = 113,
  709.   UNW_ARM_WR2 = 114,
  710.   UNW_ARM_WR3 = 115,
  711.   UNW_ARM_WR4 = 116,
  712.   UNW_ARM_WR5 = 117,
  713.   UNW_ARM_WR6 = 118,
  714.   UNW_ARM_WR7 = 119,
  715.   UNW_ARM_WR8 = 120,
  716.   UNW_ARM_WR9 = 121,
  717.   UNW_ARM_WR10 = 122,
  718.   UNW_ARM_WR11 = 123,
  719.   UNW_ARM_WR12 = 124,
  720.   UNW_ARM_WR13 = 125,
  721.   UNW_ARM_WR14 = 126,
  722.   UNW_ARM_WR15 = 127,
  723.   // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
  724.   // 134-142 -- Reserved
  725.   UNW_ARM_RA_AUTH_CODE = 143,
  726.   // 144-150 -- R8_USR-R14_USR
  727.   // 151-157 -- R8_FIQ-R14_FIQ
  728.   // 158-159 -- R13_IRQ-R14_IRQ
  729.   // 160-161 -- R13_ABT-R14_ABT
  730.   // 162-163 -- R13_UND-R14_UND
  731.   // 164-165 -- R13_SVC-R14_SVC
  732.   // 166-191 -- Reserved
  733.   UNW_ARM_WC0 = 192,
  734.   UNW_ARM_WC1 = 193,
  735.   UNW_ARM_WC2 = 194,
  736.   UNW_ARM_WC3 = 195,
  737.   // 196-199 -- wC4-wC7 (Intel wireless MMX control)
  738.   // 200-255 -- Reserved
  739.   UNW_ARM_D0  = 256,
  740.   UNW_ARM_D1  = 257,
  741.   UNW_ARM_D2  = 258,
  742.   UNW_ARM_D3  = 259,
  743.   UNW_ARM_D4  = 260,
  744.   UNW_ARM_D5  = 261,
  745.   UNW_ARM_D6  = 262,
  746.   UNW_ARM_D7  = 263,
  747.   UNW_ARM_D8  = 264,
  748.   UNW_ARM_D9  = 265,
  749.   UNW_ARM_D10 = 266,
  750.   UNW_ARM_D11 = 267,
  751.   UNW_ARM_D12 = 268,
  752.   UNW_ARM_D13 = 269,
  753.   UNW_ARM_D14 = 270,
  754.   UNW_ARM_D15 = 271,
  755.   UNW_ARM_D16 = 272,
  756.   UNW_ARM_D17 = 273,
  757.   UNW_ARM_D18 = 274,
  758.   UNW_ARM_D19 = 275,
  759.   UNW_ARM_D20 = 276,
  760.   UNW_ARM_D21 = 277,
  761.   UNW_ARM_D22 = 278,
  762.   UNW_ARM_D23 = 279,
  763.   UNW_ARM_D24 = 280,
  764.   UNW_ARM_D25 = 281,
  765.   UNW_ARM_D26 = 282,
  766.   UNW_ARM_D27 = 283,
  767.   UNW_ARM_D28 = 284,
  768.   UNW_ARM_D29 = 285,
  769.   UNW_ARM_D30 = 286,
  770.   UNW_ARM_D31 = 287,
  771.   // 288-319 -- Reserved for VFP/Neon
  772.   // 320-8191 -- Reserved
  773.   // 8192-16383 -- Unspecified vendor co-processor register.
  774. };
  775.  
  776. // OpenRISC1000 register numbers
  777. enum {
  778.   UNW_OR1K_R0  = 0,
  779.   UNW_OR1K_R1  = 1,
  780.   UNW_OR1K_R2  = 2,
  781.   UNW_OR1K_R3  = 3,
  782.   UNW_OR1K_R4  = 4,
  783.   UNW_OR1K_R5  = 5,
  784.   UNW_OR1K_R6  = 6,
  785.   UNW_OR1K_R7  = 7,
  786.   UNW_OR1K_R8  = 8,
  787.   UNW_OR1K_R9  = 9,
  788.   UNW_OR1K_R10 = 10,
  789.   UNW_OR1K_R11 = 11,
  790.   UNW_OR1K_R12 = 12,
  791.   UNW_OR1K_R13 = 13,
  792.   UNW_OR1K_R14 = 14,
  793.   UNW_OR1K_R15 = 15,
  794.   UNW_OR1K_R16 = 16,
  795.   UNW_OR1K_R17 = 17,
  796.   UNW_OR1K_R18 = 18,
  797.   UNW_OR1K_R19 = 19,
  798.   UNW_OR1K_R20 = 20,
  799.   UNW_OR1K_R21 = 21,
  800.   UNW_OR1K_R22 = 22,
  801.   UNW_OR1K_R23 = 23,
  802.   UNW_OR1K_R24 = 24,
  803.   UNW_OR1K_R25 = 25,
  804.   UNW_OR1K_R26 = 26,
  805.   UNW_OR1K_R27 = 27,
  806.   UNW_OR1K_R28 = 28,
  807.   UNW_OR1K_R29 = 29,
  808.   UNW_OR1K_R30 = 30,
  809.   UNW_OR1K_R31 = 31,
  810.   UNW_OR1K_EPCR = 32,
  811. };
  812.  
  813. // MIPS registers
  814. enum {
  815.   UNW_MIPS_R0  = 0,
  816.   UNW_MIPS_R1  = 1,
  817.   UNW_MIPS_R2  = 2,
  818.   UNW_MIPS_R3  = 3,
  819.   UNW_MIPS_R4  = 4,
  820.   UNW_MIPS_R5  = 5,
  821.   UNW_MIPS_R6  = 6,
  822.   UNW_MIPS_R7  = 7,
  823.   UNW_MIPS_R8  = 8,
  824.   UNW_MIPS_R9  = 9,
  825.   UNW_MIPS_R10 = 10,
  826.   UNW_MIPS_R11 = 11,
  827.   UNW_MIPS_R12 = 12,
  828.   UNW_MIPS_R13 = 13,
  829.   UNW_MIPS_R14 = 14,
  830.   UNW_MIPS_R15 = 15,
  831.   UNW_MIPS_R16 = 16,
  832.   UNW_MIPS_R17 = 17,
  833.   UNW_MIPS_R18 = 18,
  834.   UNW_MIPS_R19 = 19,
  835.   UNW_MIPS_R20 = 20,
  836.   UNW_MIPS_R21 = 21,
  837.   UNW_MIPS_R22 = 22,
  838.   UNW_MIPS_R23 = 23,
  839.   UNW_MIPS_R24 = 24,
  840.   UNW_MIPS_R25 = 25,
  841.   UNW_MIPS_R26 = 26,
  842.   UNW_MIPS_R27 = 27,
  843.   UNW_MIPS_R28 = 28,
  844.   UNW_MIPS_R29 = 29,
  845.   UNW_MIPS_R30 = 30,
  846.   UNW_MIPS_R31 = 31,
  847.   UNW_MIPS_F0  = 32,
  848.   UNW_MIPS_F1  = 33,
  849.   UNW_MIPS_F2  = 34,
  850.   UNW_MIPS_F3  = 35,
  851.   UNW_MIPS_F4  = 36,
  852.   UNW_MIPS_F5  = 37,
  853.   UNW_MIPS_F6  = 38,
  854.   UNW_MIPS_F7  = 39,
  855.   UNW_MIPS_F8  = 40,
  856.   UNW_MIPS_F9  = 41,
  857.   UNW_MIPS_F10 = 42,
  858.   UNW_MIPS_F11 = 43,
  859.   UNW_MIPS_F12 = 44,
  860.   UNW_MIPS_F13 = 45,
  861.   UNW_MIPS_F14 = 46,
  862.   UNW_MIPS_F15 = 47,
  863.   UNW_MIPS_F16 = 48,
  864.   UNW_MIPS_F17 = 49,
  865.   UNW_MIPS_F18 = 50,
  866.   UNW_MIPS_F19 = 51,
  867.   UNW_MIPS_F20 = 52,
  868.   UNW_MIPS_F21 = 53,
  869.   UNW_MIPS_F22 = 54,
  870.   UNW_MIPS_F23 = 55,
  871.   UNW_MIPS_F24 = 56,
  872.   UNW_MIPS_F25 = 57,
  873.   UNW_MIPS_F26 = 58,
  874.   UNW_MIPS_F27 = 59,
  875.   UNW_MIPS_F28 = 60,
  876.   UNW_MIPS_F29 = 61,
  877.   UNW_MIPS_F30 = 62,
  878.   UNW_MIPS_F31 = 63,
  879.   UNW_MIPS_HI = 64,
  880.   UNW_MIPS_LO = 65,
  881. };
  882.  
  883. // SPARC registers
  884. enum {
  885.   UNW_SPARC_G0 = 0,
  886.   UNW_SPARC_G1 = 1,
  887.   UNW_SPARC_G2 = 2,
  888.   UNW_SPARC_G3 = 3,
  889.   UNW_SPARC_G4 = 4,
  890.   UNW_SPARC_G5 = 5,
  891.   UNW_SPARC_G6 = 6,
  892.   UNW_SPARC_G7 = 7,
  893.   UNW_SPARC_O0 = 8,
  894.   UNW_SPARC_O1 = 9,
  895.   UNW_SPARC_O2 = 10,
  896.   UNW_SPARC_O3 = 11,
  897.   UNW_SPARC_O4 = 12,
  898.   UNW_SPARC_O5 = 13,
  899.   UNW_SPARC_O6 = 14,
  900.   UNW_SPARC_O7 = 15,
  901.   UNW_SPARC_L0 = 16,
  902.   UNW_SPARC_L1 = 17,
  903.   UNW_SPARC_L2 = 18,
  904.   UNW_SPARC_L3 = 19,
  905.   UNW_SPARC_L4 = 20,
  906.   UNW_SPARC_L5 = 21,
  907.   UNW_SPARC_L6 = 22,
  908.   UNW_SPARC_L7 = 23,
  909.   UNW_SPARC_I0 = 24,
  910.   UNW_SPARC_I1 = 25,
  911.   UNW_SPARC_I2 = 26,
  912.   UNW_SPARC_I3 = 27,
  913.   UNW_SPARC_I4 = 28,
  914.   UNW_SPARC_I5 = 29,
  915.   UNW_SPARC_I6 = 30,
  916.   UNW_SPARC_I7 = 31,
  917. };
  918.  
  919. // Hexagon register numbers
  920. enum {
  921.   UNW_HEXAGON_R0,
  922.   UNW_HEXAGON_R1,
  923.   UNW_HEXAGON_R2,
  924.   UNW_HEXAGON_R3,
  925.   UNW_HEXAGON_R4,
  926.   UNW_HEXAGON_R5,
  927.   UNW_HEXAGON_R6,
  928.   UNW_HEXAGON_R7,
  929.   UNW_HEXAGON_R8,
  930.   UNW_HEXAGON_R9,
  931.   UNW_HEXAGON_R10,
  932.   UNW_HEXAGON_R11,
  933.   UNW_HEXAGON_R12,
  934.   UNW_HEXAGON_R13,
  935.   UNW_HEXAGON_R14,
  936.   UNW_HEXAGON_R15,
  937.   UNW_HEXAGON_R16,
  938.   UNW_HEXAGON_R17,
  939.   UNW_HEXAGON_R18,
  940.   UNW_HEXAGON_R19,
  941.   UNW_HEXAGON_R20,
  942.   UNW_HEXAGON_R21,
  943.   UNW_HEXAGON_R22,
  944.   UNW_HEXAGON_R23,
  945.   UNW_HEXAGON_R24,
  946.   UNW_HEXAGON_R25,
  947.   UNW_HEXAGON_R26,
  948.   UNW_HEXAGON_R27,
  949.   UNW_HEXAGON_R28,
  950.   UNW_HEXAGON_R29,
  951.   UNW_HEXAGON_R30,
  952.   UNW_HEXAGON_R31,
  953.   UNW_HEXAGON_P3_0,
  954.   UNW_HEXAGON_PC,
  955. };
  956.  
  957. // RISC-V registers. These match the DWARF register numbers defined by section
  958. // 4 of the RISC-V ELF psABI specification, which can be found at:
  959. //
  960. // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
  961. enum {
  962.   UNW_RISCV_X0  = 0,
  963.   UNW_RISCV_X1  = 1,
  964.   UNW_RISCV_X2  = 2,
  965.   UNW_RISCV_X3  = 3,
  966.   UNW_RISCV_X4  = 4,
  967.   UNW_RISCV_X5  = 5,
  968.   UNW_RISCV_X6  = 6,
  969.   UNW_RISCV_X7  = 7,
  970.   UNW_RISCV_X8  = 8,
  971.   UNW_RISCV_X9  = 9,
  972.   UNW_RISCV_X10 = 10,
  973.   UNW_RISCV_X11 = 11,
  974.   UNW_RISCV_X12 = 12,
  975.   UNW_RISCV_X13 = 13,
  976.   UNW_RISCV_X14 = 14,
  977.   UNW_RISCV_X15 = 15,
  978.   UNW_RISCV_X16 = 16,
  979.   UNW_RISCV_X17 = 17,
  980.   UNW_RISCV_X18 = 18,
  981.   UNW_RISCV_X19 = 19,
  982.   UNW_RISCV_X20 = 20,
  983.   UNW_RISCV_X21 = 21,
  984.   UNW_RISCV_X22 = 22,
  985.   UNW_RISCV_X23 = 23,
  986.   UNW_RISCV_X24 = 24,
  987.   UNW_RISCV_X25 = 25,
  988.   UNW_RISCV_X26 = 26,
  989.   UNW_RISCV_X27 = 27,
  990.   UNW_RISCV_X28 = 28,
  991.   UNW_RISCV_X29 = 29,
  992.   UNW_RISCV_X30 = 30,
  993.   UNW_RISCV_X31 = 31,
  994.   UNW_RISCV_F0  = 32,
  995.   UNW_RISCV_F1  = 33,
  996.   UNW_RISCV_F2  = 34,
  997.   UNW_RISCV_F3  = 35,
  998.   UNW_RISCV_F4  = 36,
  999.   UNW_RISCV_F5  = 37,
  1000.   UNW_RISCV_F6  = 38,
  1001.   UNW_RISCV_F7  = 39,
  1002.   UNW_RISCV_F8  = 40,
  1003.   UNW_RISCV_F9  = 41,
  1004.   UNW_RISCV_F10 = 42,
  1005.   UNW_RISCV_F11 = 43,
  1006.   UNW_RISCV_F12 = 44,
  1007.   UNW_RISCV_F13 = 45,
  1008.   UNW_RISCV_F14 = 46,
  1009.   UNW_RISCV_F15 = 47,
  1010.   UNW_RISCV_F16 = 48,
  1011.   UNW_RISCV_F17 = 49,
  1012.   UNW_RISCV_F18 = 50,
  1013.   UNW_RISCV_F19 = 51,
  1014.   UNW_RISCV_F20 = 52,
  1015.   UNW_RISCV_F21 = 53,
  1016.   UNW_RISCV_F22 = 54,
  1017.   UNW_RISCV_F23 = 55,
  1018.   UNW_RISCV_F24 = 56,
  1019.   UNW_RISCV_F25 = 57,
  1020.   UNW_RISCV_F26 = 58,
  1021.   UNW_RISCV_F27 = 59,
  1022.   UNW_RISCV_F28 = 60,
  1023.   UNW_RISCV_F29 = 61,
  1024.   UNW_RISCV_F30 = 62,
  1025.   UNW_RISCV_F31 = 63,
  1026.   // 65-95 -- Reserved for future standard extensions
  1027.   // 96-127 -- v0-v31 (Vector registers)
  1028.   // 128-3071 -- Reserved for future standard extensions
  1029.   // 3072-4095 -- Reserved for custom extensions
  1030.   // 4096-8191 -- CSRs
  1031.   //
  1032.   // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec:
  1033.   // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model
  1034.   // VLENB DWARF number: 0x1000 + 0xC22
  1035.   UNW_RISCV_VLENB = 0x1C22,
  1036. };
  1037.  
  1038. // VE register numbers
  1039. enum {
  1040.   UNW_VE_S0   = 0,
  1041.   UNW_VE_S1   = 1,
  1042.   UNW_VE_S2   = 2,
  1043.   UNW_VE_S3   = 3,
  1044.   UNW_VE_S4   = 4,
  1045.   UNW_VE_S5   = 5,
  1046.   UNW_VE_S6   = 6,
  1047.   UNW_VE_S7   = 7,
  1048.   UNW_VE_S8   = 8,
  1049.   UNW_VE_S9   = 9,
  1050.   UNW_VE_S10  = 10,
  1051.   UNW_VE_S11  = 11,
  1052.   UNW_VE_S12  = 12,
  1053.   UNW_VE_S13  = 13,
  1054.   UNW_VE_S14  = 14,
  1055.   UNW_VE_S15  = 15,
  1056.   UNW_VE_S16  = 16,
  1057.   UNW_VE_S17  = 17,
  1058.   UNW_VE_S18  = 18,
  1059.   UNW_VE_S19  = 19,
  1060.   UNW_VE_S20  = 20,
  1061.   UNW_VE_S21  = 21,
  1062.   UNW_VE_S22  = 22,
  1063.   UNW_VE_S23  = 23,
  1064.   UNW_VE_S24  = 24,
  1065.   UNW_VE_S25  = 25,
  1066.   UNW_VE_S26  = 26,
  1067.   UNW_VE_S27  = 27,
  1068.   UNW_VE_S28  = 28,
  1069.   UNW_VE_S29  = 29,
  1070.   UNW_VE_S30  = 30,
  1071.   UNW_VE_S31  = 31,
  1072.   UNW_VE_S32  = 32,
  1073.   UNW_VE_S33  = 33,
  1074.   UNW_VE_S34  = 34,
  1075.   UNW_VE_S35  = 35,
  1076.   UNW_VE_S36  = 36,
  1077.   UNW_VE_S37  = 37,
  1078.   UNW_VE_S38  = 38,
  1079.   UNW_VE_S39  = 39,
  1080.   UNW_VE_S40  = 40,
  1081.   UNW_VE_S41  = 41,
  1082.   UNW_VE_S42  = 42,
  1083.   UNW_VE_S43  = 43,
  1084.   UNW_VE_S44  = 44,
  1085.   UNW_VE_S45  = 45,
  1086.   UNW_VE_S46  = 46,
  1087.   UNW_VE_S47  = 47,
  1088.   UNW_VE_S48  = 48,
  1089.   UNW_VE_S49  = 49,
  1090.   UNW_VE_S50  = 50,
  1091.   UNW_VE_S51  = 51,
  1092.   UNW_VE_S52  = 52,
  1093.   UNW_VE_S53  = 53,
  1094.   UNW_VE_S54  = 54,
  1095.   UNW_VE_S55  = 55,
  1096.   UNW_VE_S56  = 56,
  1097.   UNW_VE_S57  = 57,
  1098.   UNW_VE_S58  = 58,
  1099.   UNW_VE_S59  = 59,
  1100.   UNW_VE_S60  = 60,
  1101.   UNW_VE_S61  = 61,
  1102.   UNW_VE_S62  = 62,
  1103.   UNW_VE_S63  = 63,
  1104.   UNW_VE_V0   = 64 + 0,
  1105.   UNW_VE_V1   = 64 + 1,
  1106.   UNW_VE_V2   = 64 + 2,
  1107.   UNW_VE_V3   = 64 + 3,
  1108.   UNW_VE_V4   = 64 + 4,
  1109.   UNW_VE_V5   = 64 + 5,
  1110.   UNW_VE_V6   = 64 + 6,
  1111.   UNW_VE_V7   = 64 + 7,
  1112.   UNW_VE_V8   = 64 + 8,
  1113.   UNW_VE_V9   = 64 + 9,
  1114.   UNW_VE_V10  = 64 + 10,
  1115.   UNW_VE_V11  = 64 + 11,
  1116.   UNW_VE_V12  = 64 + 12,
  1117.   UNW_VE_V13  = 64 + 13,
  1118.   UNW_VE_V14  = 64 + 14,
  1119.   UNW_VE_V15  = 64 + 15,
  1120.   UNW_VE_V16  = 64 + 16,
  1121.   UNW_VE_V17  = 64 + 17,
  1122.   UNW_VE_V18  = 64 + 18,
  1123.   UNW_VE_V19  = 64 + 19,
  1124.   UNW_VE_V20  = 64 + 20,
  1125.   UNW_VE_V21  = 64 + 21,
  1126.   UNW_VE_V22  = 64 + 22,
  1127.   UNW_VE_V23  = 64 + 23,
  1128.   UNW_VE_V24  = 64 + 24,
  1129.   UNW_VE_V25  = 64 + 25,
  1130.   UNW_VE_V26  = 64 + 26,
  1131.   UNW_VE_V27  = 64 + 27,
  1132.   UNW_VE_V28  = 64 + 28,
  1133.   UNW_VE_V29  = 64 + 29,
  1134.   UNW_VE_V30  = 64 + 30,
  1135.   UNW_VE_V31  = 64 + 31,
  1136.   UNW_VE_V32  = 64 + 32,
  1137.   UNW_VE_V33  = 64 + 33,
  1138.   UNW_VE_V34  = 64 + 34,
  1139.   UNW_VE_V35  = 64 + 35,
  1140.   UNW_VE_V36  = 64 + 36,
  1141.   UNW_VE_V37  = 64 + 37,
  1142.   UNW_VE_V38  = 64 + 38,
  1143.   UNW_VE_V39  = 64 + 39,
  1144.   UNW_VE_V40  = 64 + 40,
  1145.   UNW_VE_V41  = 64 + 41,
  1146.   UNW_VE_V42  = 64 + 42,
  1147.   UNW_VE_V43  = 64 + 43,
  1148.   UNW_VE_V44  = 64 + 44,
  1149.   UNW_VE_V45  = 64 + 45,
  1150.   UNW_VE_V46  = 64 + 46,
  1151.   UNW_VE_V47  = 64 + 47,
  1152.   UNW_VE_V48  = 64 + 48,
  1153.   UNW_VE_V49  = 64 + 49,
  1154.   UNW_VE_V50  = 64 + 50,
  1155.   UNW_VE_V51  = 64 + 51,
  1156.   UNW_VE_V52  = 64 + 52,
  1157.   UNW_VE_V53  = 64 + 53,
  1158.   UNW_VE_V54  = 64 + 54,
  1159.   UNW_VE_V55  = 64 + 55,
  1160.   UNW_VE_V56  = 64 + 56,
  1161.   UNW_VE_V57  = 64 + 57,
  1162.   UNW_VE_V58  = 64 + 58,
  1163.   UNW_VE_V59  = 64 + 59,
  1164.   UNW_VE_V60  = 64 + 60,
  1165.   UNW_VE_V61  = 64 + 61,
  1166.   UNW_VE_V62  = 64 + 62,
  1167.   UNW_VE_V63  = 64 + 63,
  1168.   UNW_VE_VM0  = 128 + 0,
  1169.   UNW_VE_VM1  = 128 + 1,
  1170.   UNW_VE_VM2  = 128 + 2,
  1171.   UNW_VE_VM3  = 128 + 3,
  1172.   UNW_VE_VM4  = 128 + 4,
  1173.   UNW_VE_VM5  = 128 + 5,
  1174.   UNW_VE_VM6  = 128 + 6,
  1175.   UNW_VE_VM7  = 128 + 7,
  1176.   UNW_VE_VM8  = 128 + 8,
  1177.   UNW_VE_VM9  = 128 + 9,
  1178.   UNW_VE_VM10 = 128 + 10,
  1179.   UNW_VE_VM11 = 128 + 11,
  1180.   UNW_VE_VM12 = 128 + 12,
  1181.   UNW_VE_VM13 = 128 + 13,
  1182.   UNW_VE_VM14 = 128 + 14,
  1183.   UNW_VE_VM15 = 128 + 15, // = 143
  1184.  
  1185.   // Following registers don't have DWARF register numbers.
  1186.   UNW_VE_VIXR = 144,
  1187.   UNW_VE_VL   = 145,
  1188. };
  1189.  
  1190. // s390x register numbers
  1191. enum {
  1192.   UNW_S390X_R0      = 0,
  1193.   UNW_S390X_R1      = 1,
  1194.   UNW_S390X_R2      = 2,
  1195.   UNW_S390X_R3      = 3,
  1196.   UNW_S390X_R4      = 4,
  1197.   UNW_S390X_R5      = 5,
  1198.   UNW_S390X_R6      = 6,
  1199.   UNW_S390X_R7      = 7,
  1200.   UNW_S390X_R8      = 8,
  1201.   UNW_S390X_R9      = 9,
  1202.   UNW_S390X_R10     = 10,
  1203.   UNW_S390X_R11     = 11,
  1204.   UNW_S390X_R12     = 12,
  1205.   UNW_S390X_R13     = 13,
  1206.   UNW_S390X_R14     = 14,
  1207.   UNW_S390X_R15     = 15,
  1208.   UNW_S390X_F0      = 16,
  1209.   UNW_S390X_F2      = 17,
  1210.   UNW_S390X_F4      = 18,
  1211.   UNW_S390X_F6      = 19,
  1212.   UNW_S390X_F1      = 20,
  1213.   UNW_S390X_F3      = 21,
  1214.   UNW_S390X_F5      = 22,
  1215.   UNW_S390X_F7      = 23,
  1216.   UNW_S390X_F8      = 24,
  1217.   UNW_S390X_F10     = 25,
  1218.   UNW_S390X_F12     = 26,
  1219.   UNW_S390X_F14     = 27,
  1220.   UNW_S390X_F9      = 28,
  1221.   UNW_S390X_F11     = 29,
  1222.   UNW_S390X_F13     = 30,
  1223.   UNW_S390X_F15     = 31,
  1224.   // 32-47 Control Registers
  1225.   // 48-63 Access Registers
  1226.   UNW_S390X_PSWM    = 64,
  1227.   UNW_S390X_PSWA    = 65,
  1228.   // 66-67 Reserved
  1229.   // 68-83 Vector Registers %v16-%v31
  1230. };
  1231.  
  1232. // LoongArch registers.
  1233. enum {
  1234.   UNW_LOONGARCH_R0 = 0,
  1235.   UNW_LOONGARCH_R1 = 1,
  1236.   UNW_LOONGARCH_R2 = 2,
  1237.   UNW_LOONGARCH_R3 = 3,
  1238.   UNW_LOONGARCH_R4 = 4,
  1239.   UNW_LOONGARCH_R5 = 5,
  1240.   UNW_LOONGARCH_R6 = 6,
  1241.   UNW_LOONGARCH_R7 = 7,
  1242.   UNW_LOONGARCH_R8 = 8,
  1243.   UNW_LOONGARCH_R9 = 9,
  1244.   UNW_LOONGARCH_R10 = 10,
  1245.   UNW_LOONGARCH_R11 = 11,
  1246.   UNW_LOONGARCH_R12 = 12,
  1247.   UNW_LOONGARCH_R13 = 13,
  1248.   UNW_LOONGARCH_R14 = 14,
  1249.   UNW_LOONGARCH_R15 = 15,
  1250.   UNW_LOONGARCH_R16 = 16,
  1251.   UNW_LOONGARCH_R17 = 17,
  1252.   UNW_LOONGARCH_R18 = 18,
  1253.   UNW_LOONGARCH_R19 = 19,
  1254.   UNW_LOONGARCH_R20 = 20,
  1255.   UNW_LOONGARCH_R21 = 21,
  1256.   UNW_LOONGARCH_R22 = 22,
  1257.   UNW_LOONGARCH_R23 = 23,
  1258.   UNW_LOONGARCH_R24 = 24,
  1259.   UNW_LOONGARCH_R25 = 25,
  1260.   UNW_LOONGARCH_R26 = 26,
  1261.   UNW_LOONGARCH_R27 = 27,
  1262.   UNW_LOONGARCH_R28 = 28,
  1263.   UNW_LOONGARCH_R29 = 29,
  1264.   UNW_LOONGARCH_R30 = 30,
  1265.   UNW_LOONGARCH_R31 = 31,
  1266.   UNW_LOONGARCH_F0 = 32,
  1267.   UNW_LOONGARCH_F1 = 33,
  1268.   UNW_LOONGARCH_F2 = 34,
  1269.   UNW_LOONGARCH_F3 = 35,
  1270.   UNW_LOONGARCH_F4 = 36,
  1271.   UNW_LOONGARCH_F5 = 37,
  1272.   UNW_LOONGARCH_F6 = 38,
  1273.   UNW_LOONGARCH_F7 = 39,
  1274.   UNW_LOONGARCH_F8 = 40,
  1275.   UNW_LOONGARCH_F9 = 41,
  1276.   UNW_LOONGARCH_F10 = 42,
  1277.   UNW_LOONGARCH_F11 = 43,
  1278.   UNW_LOONGARCH_F12 = 44,
  1279.   UNW_LOONGARCH_F13 = 45,
  1280.   UNW_LOONGARCH_F14 = 46,
  1281.   UNW_LOONGARCH_F15 = 47,
  1282.   UNW_LOONGARCH_F16 = 48,
  1283.   UNW_LOONGARCH_F17 = 49,
  1284.   UNW_LOONGARCH_F18 = 50,
  1285.   UNW_LOONGARCH_F19 = 51,
  1286.   UNW_LOONGARCH_F20 = 52,
  1287.   UNW_LOONGARCH_F21 = 53,
  1288.   UNW_LOONGARCH_F22 = 54,
  1289.   UNW_LOONGARCH_F23 = 55,
  1290.   UNW_LOONGARCH_F24 = 56,
  1291.   UNW_LOONGARCH_F25 = 57,
  1292.   UNW_LOONGARCH_F26 = 58,
  1293.   UNW_LOONGARCH_F27 = 59,
  1294.   UNW_LOONGARCH_F28 = 60,
  1295.   UNW_LOONGARCH_F29 = 61,
  1296.   UNW_LOONGARCH_F30 = 62,
  1297.   UNW_LOONGARCH_F31 = 63,
  1298. };
  1299.  
  1300. #endif
  1301.