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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | /*===---- htmintrin.h - Standard header for PowerPC HTM ---------------===*\ |
| 2 | * |
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| 3 | * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | * See https://llvm.org/LICENSE.txt for license information. |
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| 5 | * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | * |
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| 7 | \*===----------------------------------------------------------------------===*/ |
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| 8 | |||
| 9 | #ifndef __HTMINTRIN_H |
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| 10 | #define __HTMINTRIN_H |
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| 11 | |||
| 12 | #ifndef __HTM__ |
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| 13 | #error "HTM instruction set not enabled" |
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| 14 | #endif |
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| 15 | |||
| 16 | #ifdef __powerpc__ |
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| 17 | |||
| 18 | #include <stdint.h> |
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| 19 | |||
| 20 | typedef uint64_t texasr_t; |
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| 21 | typedef uint32_t texasru_t; |
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| 22 | typedef uint32_t texasrl_t; |
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| 23 | typedef uintptr_t tfiar_t; |
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| 24 | typedef uintptr_t tfhar_t; |
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| 25 | |||
| 26 | #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) |
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| 27 | #define _HTM_NONTRANSACTIONAL 0x0 |
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| 28 | #define _HTM_SUSPENDED 0x1 |
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| 29 | #define _HTM_TRANSACTIONAL 0x2 |
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| 30 | |||
| 31 | #define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ |
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| 32 | (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1)) |
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| 33 | #define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ |
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| 34 | (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1)) |
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| 35 | |||
| 36 | #define _TEXASR_FAILURE_CODE(TEXASR) \ |
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| 37 | _TEXASR_EXTRACT_BITS(TEXASR, 7, 8) |
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| 38 | #define _TEXASRU_FAILURE_CODE(TEXASRU) \ |
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| 39 | _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8) |
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| 40 | |||
| 41 | #define _TEXASR_FAILURE_PERSISTENT(TEXASR) \ |
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| 42 | _TEXASR_EXTRACT_BITS(TEXASR, 7, 1) |
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| 43 | #define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \ |
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| 44 | _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1) |
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| 45 | |||
| 46 | #define _TEXASR_DISALLOWED(TEXASR) \ |
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| 47 | _TEXASR_EXTRACT_BITS(TEXASR, 8, 1) |
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| 48 | #define _TEXASRU_DISALLOWED(TEXASRU) \ |
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| 49 | _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1) |
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| 50 | |||
| 51 | #define _TEXASR_NESTING_OVERFLOW(TEXASR) \ |
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| 52 | _TEXASR_EXTRACT_BITS(TEXASR, 9, 1) |
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| 53 | #define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \ |
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| 54 | _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1) |
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| 55 | |||
| 56 | #define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \ |
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| 57 | _TEXASR_EXTRACT_BITS(TEXASR, 10, 1) |
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| 58 | #define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \ |
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| 59 | _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1) |
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| 60 | |||
| 61 | #define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \ |
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| 62 | _TEXASR_EXTRACT_BITS(TEXASR, 11, 1) |
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| 63 | #define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \ |
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| 64 | _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1) |
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| 65 | |||
| 66 | #define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \ |
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| 67 | _TEXASR_EXTRACT_BITS(TEXASR, 12, 1) |
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| 68 | #define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \ |
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| 69 | _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1) |
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| 70 | |||
| 71 | #define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \ |
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| 72 | _TEXASR_EXTRACT_BITS(TEXASR, 13, 1) |
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| 73 | #define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \ |
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| 74 | _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1) |
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| 75 | |||
| 76 | #define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \ |
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| 77 | _TEXASR_EXTRACT_BITS(TEXASR, 14, 1) |
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| 78 | #define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \ |
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| 79 | _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1) |
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| 80 | |||
| 81 | #define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \ |
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| 82 | _TEXASR_EXTRACT_BITS(TEXASR, 15, 1) |
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| 83 | #define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \ |
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| 84 | _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1) |
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| 85 | |||
| 86 | #define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \ |
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| 87 | _TEXASR_EXTRACT_BITS(TEXASR, 16, 1) |
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| 88 | #define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \ |
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| 89 | _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1) |
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| 90 | |||
| 91 | #define _TEXASR_ABORT(TEXASR) \ |
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| 92 | _TEXASR_EXTRACT_BITS(TEXASR, 31, 1) |
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| 93 | #define _TEXASRU_ABORT(TEXASRU) \ |
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| 94 | _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1) |
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| 95 | |||
| 96 | |||
| 97 | #define _TEXASR_SUSPENDED(TEXASR) \ |
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| 98 | _TEXASR_EXTRACT_BITS(TEXASR, 32, 1) |
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| 99 | |||
| 100 | #define _TEXASR_PRIVILEGE(TEXASR) \ |
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| 101 | _TEXASR_EXTRACT_BITS(TEXASR, 35, 2) |
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| 102 | |||
| 103 | #define _TEXASR_FAILURE_SUMMARY(TEXASR) \ |
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| 104 | _TEXASR_EXTRACT_BITS(TEXASR, 36, 1) |
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| 105 | |||
| 106 | #define _TEXASR_TFIAR_EXACT(TEXASR) \ |
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| 107 | _TEXASR_EXTRACT_BITS(TEXASR, 37, 1) |
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| 108 | |||
| 109 | #define _TEXASR_ROT(TEXASR) \ |
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| 110 | _TEXASR_EXTRACT_BITS(TEXASR, 38, 1) |
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| 111 | |||
| 112 | #define _TEXASR_TRANSACTION_LEVEL(TEXASR) \ |
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| 113 | _TEXASR_EXTRACT_BITS(TEXASR, 63, 12) |
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| 114 | |||
| 115 | #endif /* __powerpc */ |
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| 116 | |||
| 117 | #ifdef __s390__ |
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| 118 | |||
| 119 | /* Condition codes generated by tbegin */ |
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| 120 | #define _HTM_TBEGIN_STARTED 0 |
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| 121 | #define _HTM_TBEGIN_INDETERMINATE 1 |
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| 122 | #define _HTM_TBEGIN_TRANSIENT 2 |
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| 123 | #define _HTM_TBEGIN_PERSISTENT 3 |
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| 124 | |||
| 125 | /* The abort codes below this threshold are reserved for machine use. */ |
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| 126 | #define _HTM_FIRST_USER_ABORT_CODE 256 |
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| 127 | |||
| 128 | /* The transaction diagnostic block is it is defined in the Principles |
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| 129 | of Operation chapter 5-91. */ |
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| 130 | |||
| 131 | struct __htm_tdb { |
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| 132 | unsigned char format; /* 0 */ |
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| 133 | unsigned char flags; |
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| 134 | unsigned char reserved1[4]; |
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| 135 | unsigned short nesting_depth; |
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| 136 | unsigned long long abort_code; /* 8 */ |
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| 137 | unsigned long long conflict_token; /* 16 */ |
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| 138 | unsigned long long atia; /* 24 */ |
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| 139 | unsigned char eaid; /* 32 */ |
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| 140 | unsigned char dxc; |
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| 141 | unsigned char reserved2[2]; |
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| 142 | unsigned int program_int_id; |
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| 143 | unsigned long long exception_id; /* 40 */ |
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| 144 | unsigned long long bea; /* 48 */ |
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| 145 | unsigned char reserved3[72]; /* 56 */ |
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| 146 | unsigned long long gprs[16]; /* 128 */ |
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| 147 | } __attribute__((__packed__, __aligned__ (8))); |
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| 148 | |||
| 149 | |||
| 150 | /* Helper intrinsics to retry tbegin in case of transient failure. */ |
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| 151 | |||
| 152 | static __inline int __attribute__((__always_inline__, __nodebug__)) |
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| 153 | __builtin_tbegin_retry_null (int __retry) |
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| 154 | { |
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| 155 | int cc, i = 0; |
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| 156 | |||
| 157 | while ((cc = __builtin_tbegin(0)) == _HTM_TBEGIN_TRANSIENT |
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| 158 | && i++ < __retry) |
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| 159 | __builtin_tx_assist(i); |
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| 160 | |||
| 161 | return cc; |
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| 162 | } |
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| 163 | |||
| 164 | static __inline int __attribute__((__always_inline__, __nodebug__)) |
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| 165 | __builtin_tbegin_retry_tdb (void *__tdb, int __retry) |
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| 166 | { |
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| 167 | int cc, i = 0; |
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| 168 | |||
| 169 | while ((cc = __builtin_tbegin(__tdb)) == _HTM_TBEGIN_TRANSIENT |
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| 170 | && i++ < __retry) |
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| 171 | __builtin_tx_assist(i); |
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| 172 | |||
| 173 | return cc; |
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| 174 | } |
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| 175 | |||
| 176 | #define __builtin_tbegin_retry(tdb, retry) \ |
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| 177 | (__builtin_constant_p(tdb == 0) && tdb == 0 ? \ |
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| 178 | __builtin_tbegin_retry_null(retry) : \ |
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| 179 | __builtin_tbegin_retry_tdb(tdb, retry)) |
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| 180 | |||
| 181 | static __inline int __attribute__((__always_inline__, __nodebug__)) |
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| 182 | __builtin_tbegin_retry_nofloat_null (int __retry) |
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| 183 | { |
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| 184 | int cc, i = 0; |
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| 185 | |||
| 186 | while ((cc = __builtin_tbegin_nofloat(0)) == _HTM_TBEGIN_TRANSIENT |
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| 187 | && i++ < __retry) |
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| 188 | __builtin_tx_assist(i); |
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| 189 | |||
| 190 | return cc; |
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| 191 | } |
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| 192 | |||
| 193 | static __inline int __attribute__((__always_inline__, __nodebug__)) |
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| 194 | __builtin_tbegin_retry_nofloat_tdb (void *__tdb, int __retry) |
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| 195 | { |
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| 196 | int cc, i = 0; |
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| 197 | |||
| 198 | while ((cc = __builtin_tbegin_nofloat(__tdb)) == _HTM_TBEGIN_TRANSIENT |
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| 199 | && i++ < __retry) |
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| 200 | __builtin_tx_assist(i); |
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| 201 | |||
| 202 | return cc; |
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| 203 | } |
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| 204 | |||
| 205 | #define __builtin_tbegin_retry_nofloat(tdb, retry) \ |
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| 206 | (__builtin_constant_p(tdb == 0) && tdb == 0 ? \ |
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| 207 | __builtin_tbegin_retry_nofloat_null(retry) : \ |
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| 208 | __builtin_tbegin_retry_nofloat_tdb(tdb, retry)) |
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| 209 | |||
| 210 | #endif /* __s390__ */ |
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| 211 | |||
| 212 | #endif /* __HTMINTRIN_H */ |