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/*===----------------- avxifmaintrin.h - IFMA intrinsics -------------------===
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 *
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 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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 * See https://llvm.org/LICENSE.txt for license information.
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 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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 *
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 *===-----------------------------------------------------------------------===
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 */
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#ifndef __IMMINTRIN_H
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#error "Never use <avxifmaintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __AVXIFMAINTRIN_H
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#define __AVXIFMAINTRIN_H
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/* Define the default attributes for the functions in this file. */
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#define __DEFAULT_FN_ATTRS128                                                  \
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  __attribute__((__always_inline__, __nodebug__, __target__("avxifma"),        \
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                 __min_vector_width__(128)))
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#define __DEFAULT_FN_ATTRS256                                                  \
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  __attribute__((__always_inline__, __nodebug__, __target__("avxifma"),        \
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                 __min_vector_width__(256)))
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// must vex-encoding
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/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
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/// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
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/// unsigned integer from the intermediate result with the corresponding
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/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i
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/// _mm_madd52hi_avx_epu64 (__m128i __X, __m128i __Y, __m128i __Z)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPMADD52HUQ instruction.
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///
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/// \return
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///     return __m128i dst.
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/// \param __X
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///     A 128-bit vector of [2 x i64]
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/// \param __Y
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///     A 128-bit vector of [2 x i64]
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/// \param __Z
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///     A 128-bit vector of [2 x i64]
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///
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/// \code{.operation}
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/// FOR j := 0 to 1
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///     i := j*64
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///     tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
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///     dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128
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_mm_madd52hi_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z) {
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  return (__m128i)__builtin_ia32_vpmadd52huq128((__v2di)__X, (__v2di)__Y,
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                                                (__v2di)__Z);
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}
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/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
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/// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
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/// unsigned integer from the intermediate result with the corresponding
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/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i
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/// _mm256_madd52hi_avx_epu64 (__m256i __X, __m256i __Y, __m256i __Z)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPMADD52HUQ instruction.
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///
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/// \return
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///     return __m256i dst.
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/// \param __X
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///     A 256-bit vector of [4 x i64]
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/// \param __Y
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///     A 256-bit vector of [4 x i64]
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/// \param __Z
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///     A 256-bit vector of [4 x i64]
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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///     i := j*64
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///     tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
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///     dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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static __inline__ __m256i __DEFAULT_FN_ATTRS256
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_mm256_madd52hi_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z) {
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  return (__m256i)__builtin_ia32_vpmadd52huq256((__v4di)__X, (__v4di)__Y,
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                                                (__v4di)__Z);
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}
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/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
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/// and \a __Z to form a 104-bit intermediate result. Add the low 52-bit
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/// unsigned integer from the intermediate result with the corresponding
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/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i
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/// _mm_madd52lo_avx_epu64 (__m128i __X, __m128i __Y, __m128i __Z)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPMADD52LUQ instruction.
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///
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/// \return
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///     return __m128i dst.
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/// \param __X
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///     A 128-bit vector of [2 x i64]
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/// \param __Y
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///     A 128-bit vector of [2 x i64]
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/// \param __Z
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///     A 128-bit vector of [2 x i64]
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///
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/// \code{.operation}
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/// FOR j := 0 to 1
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///     i := j*64
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///     tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
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///     dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128
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_mm_madd52lo_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z) {
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  return (__m128i)__builtin_ia32_vpmadd52luq128((__v2di)__X, (__v2di)__Y,
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                                                (__v2di)__Z);
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}
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/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
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/// and \a __Z to form a 104-bit intermediate result. Add the low 52-bit
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/// unsigned integer from the intermediate result with the corresponding
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/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i
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/// _mm256_madd52lo_avx_epu64 (__m256i __X, __m256i __Y, __m256i __Z)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPMADD52LUQ instruction.
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///
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/// \return
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///     return __m256i dst.
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/// \param __X
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///     A 256-bit vector of [4 x i64]
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/// \param __Y
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///     A 256-bit vector of [4 x i64]
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/// \param __Z
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///     A 256-bit vector of [4 x i64]
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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///     i := j*64
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///     tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
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///     dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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static __inline__ __m256i __DEFAULT_FN_ATTRS256
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_mm256_madd52lo_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z) {
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  return (__m256i)__builtin_ia32_vpmadd52luq256((__v4di)__X, (__v4di)__Y,
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                                                (__v4di)__Z);
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}
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#undef __DEFAULT_FN_ATTRS128
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#undef __DEFAULT_FN_ATTRS256
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#endif // __AVXIFMAINTRIN_H