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| Rev | Author | Line No. | Line |
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| 14 | pmbaty | 1 | //===-- TargetParser - Parser for target features ---------------*- C++ -*-===// |
| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file implements a target parser to recognise hardware features such as |
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| 10 | // FPU/CPU/ARCH names as well as specific support such as HDIV, etc. |
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| 11 | // |
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| 12 | //===----------------------------------------------------------------------===// |
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| 13 | |||
| 14 | #ifndef LLVM_TARGETPARSER_TARGETPARSER_H |
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| 15 | #define LLVM_TARGETPARSER_TARGETPARSER_H |
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| 16 | |||
| 17 | #include "llvm/ADT/StringRef.h" |
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| 18 | #include <cstdint> |
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| 19 | // FIXME: vector is used because that's what clang uses for subtarget feature |
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| 20 | // lists, but SmallVector would probably be better |
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| 21 | #include <vector> |
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| 22 | |||
| 23 | namespace llvm { |
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| 24 | |||
| 25 | template <typename T> class SmallVectorImpl; |
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| 26 | class Triple; |
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| 27 | |||
| 28 | // Target specific information in their own namespaces. |
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| 29 | // (ARM/AArch64/X86 are declared in ARM/AArch64/X86TargetParser.h) |
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| 30 | // These should be generated from TableGen because the information is already |
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| 31 | // there, and there is where new information about targets will be added. |
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| 32 | // FIXME: To TableGen this we need to make some table generated files available |
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| 33 | // even if the back-end is not compiled with LLVM, plus we need to create a new |
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| 34 | // back-end to TableGen to create these clean tables. |
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| 35 | namespace AMDGPU { |
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| 36 | |||
| 37 | /// GPU kinds supported by the AMDGPU target. |
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| 38 | enum GPUKind : uint32_t { |
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| 39 | // Not specified processor. |
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| 40 | GK_NONE = 0, |
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| 41 | |||
| 42 | // R600-based processors. |
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| 43 | GK_R600 = 1, |
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| 44 | GK_R630 = 2, |
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| 45 | GK_RS880 = 3, |
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| 46 | GK_RV670 = 4, |
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| 47 | GK_RV710 = 5, |
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| 48 | GK_RV730 = 6, |
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| 49 | GK_RV770 = 7, |
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| 50 | GK_CEDAR = 8, |
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| 51 | GK_CYPRESS = 9, |
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| 52 | GK_JUNIPER = 10, |
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| 53 | GK_REDWOOD = 11, |
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| 54 | GK_SUMO = 12, |
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| 55 | GK_BARTS = 13, |
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| 56 | GK_CAICOS = 14, |
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| 57 | GK_CAYMAN = 15, |
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| 58 | GK_TURKS = 16, |
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| 59 | |||
| 60 | GK_R600_FIRST = GK_R600, |
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| 61 | GK_R600_LAST = GK_TURKS, |
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| 62 | |||
| 63 | // AMDGCN-based processors. |
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| 64 | GK_GFX600 = 32, |
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| 65 | GK_GFX601 = 33, |
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| 66 | GK_GFX602 = 34, |
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| 67 | |||
| 68 | GK_GFX700 = 40, |
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| 69 | GK_GFX701 = 41, |
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| 70 | GK_GFX702 = 42, |
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| 71 | GK_GFX703 = 43, |
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| 72 | GK_GFX704 = 44, |
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| 73 | GK_GFX705 = 45, |
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| 74 | |||
| 75 | GK_GFX801 = 50, |
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| 76 | GK_GFX802 = 51, |
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| 77 | GK_GFX803 = 52, |
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| 78 | GK_GFX805 = 53, |
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| 79 | GK_GFX810 = 54, |
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| 80 | |||
| 81 | GK_GFX900 = 60, |
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| 82 | GK_GFX902 = 61, |
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| 83 | GK_GFX904 = 62, |
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| 84 | GK_GFX906 = 63, |
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| 85 | GK_GFX908 = 64, |
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| 86 | GK_GFX909 = 65, |
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| 87 | GK_GFX90A = 66, |
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| 88 | GK_GFX90C = 67, |
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| 89 | GK_GFX940 = 68, |
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| 90 | |||
| 91 | GK_GFX1010 = 71, |
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| 92 | GK_GFX1011 = 72, |
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| 93 | GK_GFX1012 = 73, |
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| 94 | GK_GFX1013 = 74, |
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| 95 | GK_GFX1030 = 75, |
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| 96 | GK_GFX1031 = 76, |
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| 97 | GK_GFX1032 = 77, |
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| 98 | GK_GFX1033 = 78, |
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| 99 | GK_GFX1034 = 79, |
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| 100 | GK_GFX1035 = 80, |
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| 101 | GK_GFX1036 = 81, |
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| 102 | |||
| 103 | GK_GFX1100 = 90, |
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| 104 | GK_GFX1101 = 91, |
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| 105 | GK_GFX1102 = 92, |
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| 106 | GK_GFX1103 = 93, |
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| 107 | |||
| 108 | GK_AMDGCN_FIRST = GK_GFX600, |
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| 109 | GK_AMDGCN_LAST = GK_GFX1103, |
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| 110 | }; |
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| 111 | |||
| 112 | /// Instruction set architecture version. |
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| 113 | struct IsaVersion { |
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| 114 | unsigned Major; |
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| 115 | unsigned Minor; |
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| 116 | unsigned Stepping; |
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| 117 | }; |
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| 118 | |||
| 119 | // This isn't comprehensive for now, just things that are needed from the |
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| 120 | // frontend driver. |
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| 121 | enum ArchFeatureKind : uint32_t { |
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| 122 | FEATURE_NONE = 0, |
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| 123 | |||
| 124 | // These features only exist for r600, and are implied true for amdgcn. |
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| 125 | FEATURE_FMA = 1 << 1, |
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| 126 | FEATURE_LDEXP = 1 << 2, |
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| 127 | FEATURE_FP64 = 1 << 3, |
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| 128 | |||
| 129 | // Common features. |
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| 130 | FEATURE_FAST_FMA_F32 = 1 << 4, |
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| 131 | FEATURE_FAST_DENORMAL_F32 = 1 << 5, |
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| 132 | |||
| 133 | // Wavefront 32 is available. |
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| 134 | FEATURE_WAVE32 = 1 << 6, |
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| 135 | |||
| 136 | // Xnack is available. |
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| 137 | FEATURE_XNACK = 1 << 7, |
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| 138 | |||
| 139 | // Sram-ecc is available. |
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| 140 | FEATURE_SRAMECC = 1 << 8, |
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| 141 | }; |
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| 142 | |||
| 143 | StringRef getArchNameAMDGCN(GPUKind AK); |
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| 144 | StringRef getArchNameR600(GPUKind AK); |
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| 145 | StringRef getCanonicalArchName(const Triple &T, StringRef Arch); |
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| 146 | GPUKind parseArchAMDGCN(StringRef CPU); |
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| 147 | GPUKind parseArchR600(StringRef CPU); |
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| 148 | unsigned getArchAttrAMDGCN(GPUKind AK); |
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| 149 | unsigned getArchAttrR600(GPUKind AK); |
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| 150 | |||
| 151 | void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values); |
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| 152 | void fillValidArchListR600(SmallVectorImpl<StringRef> &Values); |
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| 153 | |||
| 154 | IsaVersion getIsaVersion(StringRef GPU); |
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| 155 | |||
| 156 | } // namespace AMDGPU |
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| 157 | } // namespace llvm |
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| 158 | |||
| 159 | #endif |