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| Rev | Author | Line No. | Line |
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| 14 | pmbaty | 1 | //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===// |
| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file is part of the X86 Disassembler. |
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| 10 | // It contains common definitions used by both the disassembler and the table |
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| 11 | // generator. |
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| 12 | // Documentation for the disassembler can be found in X86Disassembler.h. |
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| 13 | // |
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| 14 | //===----------------------------------------------------------------------===// |
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| 15 | |||
| 16 | #ifndef LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H |
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| 17 | #define LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H |
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| 18 | |||
| 19 | #include "llvm/Support/DataTypes.h" |
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| 20 | |||
| 21 | namespace llvm { |
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| 22 | namespace X86Disassembler { |
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| 23 | |||
| 24 | #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers |
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| 25 | #define CONTEXTS_SYM x86DisassemblerContexts |
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| 26 | #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes |
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| 27 | #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes |
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| 28 | #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes |
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| 29 | #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes |
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| 30 | #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes |
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| 31 | #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes |
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| 32 | #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes |
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| 33 | #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes |
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| 34 | #define MAP5_SYM x86DisassemblerMap5Opcodes |
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| 35 | #define MAP6_SYM x86DisassemblerMap6Opcodes |
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| 36 | |||
| 37 | #define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers" |
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| 38 | #define CONTEXTS_STR "x86DisassemblerContexts" |
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| 39 | #define ONEBYTE_STR "x86DisassemblerOneByteOpcodes" |
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| 40 | #define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes" |
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| 41 | #define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes" |
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| 42 | #define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes" |
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| 43 | #define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes" |
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| 44 | #define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes" |
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| 45 | #define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes" |
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| 46 | #define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes" |
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| 47 | #define MAP5_STR "x86DisassemblerMap5Opcodes" |
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| 48 | #define MAP6_STR "x86DisassemblerMap6Opcodes" |
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| 49 | |||
| 50 | // Attributes of an instruction that must be known before the opcode can be |
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| 51 | // processed correctly. Most of these indicate the presence of particular |
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| 52 | // prefixes, but ATTR_64BIT is simply an attribute of the decoding context. |
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| 53 | enum attributeBits { |
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| 54 | ATTR_NONE = 0x00, |
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| 55 | ATTR_64BIT = 0x1 << 0, |
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| 56 | ATTR_XS = 0x1 << 1, |
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| 57 | ATTR_XD = 0x1 << 2, |
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| 58 | ATTR_REXW = 0x1 << 3, |
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| 59 | ATTR_OPSIZE = 0x1 << 4, |
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| 60 | ATTR_ADSIZE = 0x1 << 5, |
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| 61 | ATTR_VEX = 0x1 << 6, |
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| 62 | ATTR_VEXL = 0x1 << 7, |
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| 63 | ATTR_EVEX = 0x1 << 8, |
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| 64 | ATTR_EVEXL2 = 0x1 << 9, |
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| 65 | ATTR_EVEXK = 0x1 << 10, |
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| 66 | ATTR_EVEXKZ = 0x1 << 11, |
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| 67 | ATTR_EVEXB = 0x1 << 12, |
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| 68 | ATTR_max = 0x1 << 13, |
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| 69 | }; |
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| 70 | |||
| 71 | // Combinations of the above attributes that are relevant to instruction |
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| 72 | // decode. Although other combinations are possible, they can be reduced to |
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| 73 | // these without affecting the ultimately decoded instruction. |
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| 74 | |||
| 75 | // Class name Rank Rationale for rank assignment |
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| 76 | #define INSTRUCTION_CONTEXTS \ |
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| 77 | ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ |
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| 78 | ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ |
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| 79 | "64-bit mode but no more") \ |
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| 80 | ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ |
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| 81 | "operands change width") \ |
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| 82 | ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ |
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| 83 | "operands change width") \ |
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| 84 | ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ |
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| 85 | ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ |
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| 86 | "but not the operands") \ |
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| 87 | ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ |
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| 88 | "but not the operands") \ |
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| 89 | ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ |
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| 90 | "operands change width") \ |
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| 91 | ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ |
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| 92 | "operands change width") \ |
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| 93 | ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \ |
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| 94 | "operands change width") \ |
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| 95 | ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \ |
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| 96 | "operands change width") \ |
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| 97 | ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ |
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| 98 | "change width; overrides IC_OPSIZE") \ |
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| 99 | ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ |
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| 100 | "prefix") \ |
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| 101 | ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ |
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| 102 | ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ |
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| 103 | ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ |
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| 104 | "IC_ADSIZE") \ |
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| 105 | ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ |
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| 106 | "secondary") \ |
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| 107 | ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ |
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| 108 | ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ |
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| 109 | ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ |
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| 110 | ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ |
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| 111 | ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ |
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| 112 | ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ |
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| 113 | "opcode") \ |
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| 114 | ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ |
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| 115 | "IC_64BIT_REXW_XS") \ |
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| 116 | ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ |
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| 117 | "else because this changes most " \ |
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| 118 | "operands' meaning") \ |
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| 119 | ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ |
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| 120 | ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ |
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| 121 | ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ |
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| 122 | ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ |
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| 123 | ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ |
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| 124 | ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ |
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| 125 | ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ |
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| 126 | ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ |
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| 127 | ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ |
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| 128 | ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ |
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| 129 | ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ |
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| 130 | ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ |
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| 131 | ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ |
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| 132 | ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ |
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| 133 | ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ |
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| 134 | ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ |
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| 135 | ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ |
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| 136 | ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ |
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| 137 | ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ |
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| 138 | ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ |
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| 139 | ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ |
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| 140 | ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ |
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| 141 | ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ |
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| 142 | ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ |
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| 143 | ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ |
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| 144 | ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ |
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| 145 | ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ |
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| 146 | ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ |
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| 147 | ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ |
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| 148 | ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ |
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| 149 | ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ |
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| 150 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ |
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| 151 | ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ |
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| 152 | ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ |
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| 153 | ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ |
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| 154 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ |
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| 155 | ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ |
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| 156 | ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ |
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| 157 | ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ |
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| 158 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ |
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| 159 | ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ |
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| 160 | ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ |
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| 161 | ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ |
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| 162 | ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ |
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| 163 | ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ |
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| 164 | ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ |
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| 165 | ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ |
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| 166 | ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ |
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| 167 | ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ |
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| 168 | ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ |
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| 169 | ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ |
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| 170 | ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ |
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| 171 | ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ |
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| 172 | ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ |
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| 173 | ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ |
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| 174 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ |
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| 175 | ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ |
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| 176 | ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ |
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| 177 | ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ |
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| 178 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ |
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| 179 | ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ |
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| 180 | ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ |
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| 181 | ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ |
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| 182 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ |
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| 183 | ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ |
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| 184 | ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ |
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| 185 | ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ |
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| 186 | ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ |
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| 187 | ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ |
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| 188 | ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ |
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| 189 | ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ |
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| 190 | ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ |
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| 191 | ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ |
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| 192 | ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ |
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| 193 | ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ |
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| 194 | ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ |
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| 195 | ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ |
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| 196 | ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ |
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| 197 | ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ |
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| 198 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ |
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| 199 | ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ |
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| 200 | ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ |
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| 201 | ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ |
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| 202 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ |
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| 203 | ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ |
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| 204 | ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ |
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| 205 | ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ |
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| 206 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ |
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| 207 | ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ |
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| 208 | ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ |
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| 209 | ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ |
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| 210 | ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ |
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| 211 | ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ |
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| 212 | ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ |
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| 213 | ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ |
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| 214 | ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ |
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| 215 | ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ |
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| 216 | ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ |
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| 217 | ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ |
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| 218 | ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ |
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| 219 | ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ |
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| 220 | ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ |
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| 221 | ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ |
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| 222 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ |
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| 223 | ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ |
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| 224 | ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ |
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| 225 | ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ |
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| 226 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ |
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| 227 | ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ |
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| 228 | ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ |
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| 229 | ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ |
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| 230 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ |
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| 231 | ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ |
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| 232 | ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ |
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| 233 | ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ |
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| 234 | ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ |
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| 235 | ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ |
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| 236 | ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ |
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| 237 | ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ |
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| 238 | ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ |
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| 239 | ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ |
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| 240 | ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ |
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| 241 | ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ |
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| 242 | ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ |
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| 243 | ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ |
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| 244 | ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ |
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| 245 | ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ |
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| 246 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ |
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| 247 | ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ |
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| 248 | ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ |
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| 249 | ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ |
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| 250 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ |
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| 251 | ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ |
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| 252 | ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ |
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| 253 | ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ |
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| 254 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ |
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| 255 | ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ |
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| 256 | ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ |
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| 257 | ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ |
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| 258 | ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ |
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| 259 | ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ |
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| 260 | ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ |
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| 261 | ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ |
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| 262 | ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ |
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| 263 | ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ |
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| 264 | ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ |
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| 265 | ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ |
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| 266 | ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ |
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| 267 | ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ |
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| 268 | ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ |
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| 269 | ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ |
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| 270 | ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ |
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| 271 | ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ |
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| 272 | ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ |
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| 273 | ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ |
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| 274 | ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ |
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| 275 | ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ |
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| 276 | ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ |
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| 277 | ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ |
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| 278 | ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") |
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| 279 | |||
| 280 | #define ENUM_ENTRY(n, r, d) n, |
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| 281 | enum InstructionContext { |
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| 282 | INSTRUCTION_CONTEXTS |
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| 283 | IC_max |
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| 284 | }; |
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| 285 | #undef ENUM_ENTRY |
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| 286 | |||
| 287 | // Opcode types, which determine which decode table to use, both in the Intel |
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| 288 | // manual and also for the decoder. |
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| 289 | enum OpcodeType { |
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| 290 | ONEBYTE = 0, |
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| 291 | TWOBYTE = 1, |
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| 292 | THREEBYTE_38 = 2, |
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| 293 | THREEBYTE_3A = 3, |
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| 294 | XOP8_MAP = 4, |
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| 295 | XOP9_MAP = 5, |
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| 296 | XOPA_MAP = 6, |
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| 297 | THREEDNOW_MAP = 7, |
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| 298 | MAP5 = 8, |
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| 299 | MAP6 = 9 |
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| 300 | }; |
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| 301 | |||
| 302 | // The following structs are used for the hierarchical decode table. After |
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| 303 | // determining the instruction's class (i.e., which IC_* constant applies to |
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| 304 | // it), the decoder reads the opcode. Some instructions require specific |
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| 305 | // values of the ModR/M byte, so the ModR/M byte indexes into the final table. |
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| 306 | // |
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| 307 | // If a ModR/M byte is not required, "required" is left unset, and the values |
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| 308 | // for each instructionID are identical. |
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| 309 | typedef uint16_t InstrUID; |
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| 310 | |||
| 311 | // ModRMDecisionType - describes the type of ModR/M decision, allowing the |
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| 312 | // consumer to determine the number of entries in it. |
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| 313 | // |
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| 314 | // MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded |
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| 315 | // instruction is the same. |
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| 316 | // MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode |
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| 317 | // corresponds to one instruction; otherwise, it corresponds to |
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| 318 | // a different instruction. |
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| 319 | // MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte |
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| 320 | // divided by 8 is used to select instruction; otherwise, each |
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| 321 | // value of the ModR/M byte could correspond to a different |
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| 322 | // instruction. |
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| 323 | // MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This |
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| 324 | // corresponds to instructions that use reg field as opcode |
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| 325 | // MODRM_FULL - Potentially, each value of the ModR/M byte could correspond |
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| 326 | // to a different instruction. |
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| 327 | #define MODRMTYPES \ |
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| 328 | ENUM_ENTRY(MODRM_ONEENTRY) \ |
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| 329 | ENUM_ENTRY(MODRM_SPLITRM) \ |
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| 330 | ENUM_ENTRY(MODRM_SPLITMISC) \ |
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| 331 | ENUM_ENTRY(MODRM_SPLITREG) \ |
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| 332 | ENUM_ENTRY(MODRM_FULL) |
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| 333 | |||
| 334 | #define ENUM_ENTRY(n) n, |
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| 335 | enum ModRMDecisionType { |
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| 336 | MODRMTYPES |
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| 337 | MODRM_max |
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| 338 | }; |
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| 339 | #undef ENUM_ENTRY |
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| 340 | |||
| 341 | #define CASE_ENCODING_RM \ |
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| 342 | case ENCODING_RM: \ |
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| 343 | case ENCODING_RM_CD2: \ |
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| 344 | case ENCODING_RM_CD4: \ |
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| 345 | case ENCODING_RM_CD8: \ |
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| 346 | case ENCODING_RM_CD16: \ |
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| 347 | case ENCODING_RM_CD32: \ |
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| 348 | case ENCODING_RM_CD64 |
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| 349 | |||
| 350 | #define CASE_ENCODING_VSIB \ |
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| 351 | case ENCODING_VSIB: \ |
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| 352 | case ENCODING_VSIB_CD2: \ |
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| 353 | case ENCODING_VSIB_CD4: \ |
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| 354 | case ENCODING_VSIB_CD8: \ |
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| 355 | case ENCODING_VSIB_CD16: \ |
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| 356 | case ENCODING_VSIB_CD32: \ |
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| 357 | case ENCODING_VSIB_CD64 |
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| 358 | |||
| 359 | // Physical encodings of instruction operands. |
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| 360 | #define ENCODINGS \ |
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| 361 | ENUM_ENTRY(ENCODING_NONE, "") \ |
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| 362 | ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ |
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| 363 | ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ |
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| 364 | ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ |
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| 365 | ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ |
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| 366 | ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ |
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| 367 | ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ |
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| 368 | ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ |
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| 369 | ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ |
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| 370 | ENUM_ENTRY(ENCODING_SIB, "Force SIB operand in ModR/M byte.") \ |
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| 371 | ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ |
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| 372 | ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ |
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| 373 | ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ |
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| 374 | ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ |
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| 375 | ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ |
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| 376 | ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ |
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| 377 | ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ |
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| 378 | ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ |
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| 379 | ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ |
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| 380 | ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ |
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| 381 | ENUM_ENTRY(ENCODING_IW, "2-byte") \ |
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| 382 | ENUM_ENTRY(ENCODING_ID, "4-byte") \ |
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| 383 | ENUM_ENTRY(ENCODING_IO, "8-byte") \ |
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| 384 | ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8B..R15B) Register code added to " \ |
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| 385 | "the opcode byte") \ |
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| 386 | ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ |
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| 387 | ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ |
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| 388 | ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ |
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| 389 | ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ |
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| 390 | "byte.") \ |
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| 391 | \ |
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| 392 | ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ |
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| 393 | ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ |
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| 394 | ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ |
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| 395 | ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ |
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| 396 | "opcode byte") \ |
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| 397 | ENUM_ENTRY(ENCODING_CC, "Condition code encoded in opcode") \ |
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| 398 | ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ |
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| 399 | "in type") \ |
||
| 400 | ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ |
||
| 401 | ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") |
||
| 402 | |||
| 403 | #define ENUM_ENTRY(n, d) n, |
||
| 404 | enum OperandEncoding { |
||
| 405 | ENCODINGS |
||
| 406 | ENCODING_max |
||
| 407 | }; |
||
| 408 | #undef ENUM_ENTRY |
||
| 409 | |||
| 410 | // Semantic interpretations of instruction operands. |
||
| 411 | #define TYPES \ |
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| 412 | ENUM_ENTRY(TYPE_NONE, "") \ |
||
| 413 | ENUM_ENTRY(TYPE_REL, "immediate address") \ |
||
| 414 | ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ |
||
| 415 | ENUM_ENTRY(TYPE_R16, "2-byte") \ |
||
| 416 | ENUM_ENTRY(TYPE_R32, "4-byte") \ |
||
| 417 | ENUM_ENTRY(TYPE_R64, "8-byte") \ |
||
| 418 | ENUM_ENTRY(TYPE_IMM, "immediate operand") \ |
||
| 419 | ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ |
||
| 420 | ENUM_ENTRY(TYPE_M, "Memory operand") \ |
||
| 421 | ENUM_ENTRY(TYPE_MSIB, "Memory operand force sib encoding") \ |
||
| 422 | ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ |
||
| 423 | ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ |
||
| 424 | ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ |
||
| 425 | ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ |
||
| 426 | ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ |
||
| 427 | ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ |
||
| 428 | ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ |
||
| 429 | ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ |
||
| 430 | ENUM_ENTRY(TYPE_XMM, "16-byte") \ |
||
| 431 | ENUM_ENTRY(TYPE_YMM, "32-byte") \ |
||
| 432 | ENUM_ENTRY(TYPE_ZMM, "64-byte") \ |
||
| 433 | ENUM_ENTRY(TYPE_VK, "mask register") \ |
||
| 434 | ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \ |
||
| 435 | ENUM_ENTRY(TYPE_TMM, "tile") \ |
||
| 436 | ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ |
||
| 437 | ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ |
||
| 438 | ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ |
||
| 439 | ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ |
||
| 440 | \ |
||
| 441 | ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ |
||
| 442 | ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ |
||
| 443 | ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ |
||
| 444 | ENUM_ENTRY(TYPE_DUP1, "operand 1") \ |
||
| 445 | ENUM_ENTRY(TYPE_DUP2, "operand 2") \ |
||
| 446 | ENUM_ENTRY(TYPE_DUP3, "operand 3") \ |
||
| 447 | ENUM_ENTRY(TYPE_DUP4, "operand 4") \ |
||
| 448 | |||
| 449 | #define ENUM_ENTRY(n, d) n, |
||
| 450 | enum OperandType { |
||
| 451 | TYPES |
||
| 452 | TYPE_max |
||
| 453 | }; |
||
| 454 | #undef ENUM_ENTRY |
||
| 455 | |||
| 456 | /// The specification for how to extract and interpret one operand. |
||
| 457 | struct OperandSpecifier { |
||
| 458 | uint8_t encoding; |
||
| 459 | uint8_t type; |
||
| 460 | }; |
||
| 461 | |||
| 462 | static const unsigned X86_MAX_OPERANDS = 6; |
||
| 463 | |||
| 464 | /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode |
||
| 465 | /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, |
||
| 466 | /// respectively. |
||
| 467 | enum DisassemblerMode { |
||
| 468 | MODE_16BIT, |
||
| 469 | MODE_32BIT, |
||
| 470 | MODE_64BIT |
||
| 471 | }; |
||
| 472 | |||
| 473 | } // namespace X86Disassembler |
||
| 474 | } // namespace llvm |
||
| 475 | |||
| 476 | #endif |