Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | //===---------------------------- Context.h ---------------------*- C++ -*-===// |
| 2 | // |
||
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
||
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
||
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
||
| 6 | // |
||
| 7 | //===----------------------------------------------------------------------===// |
||
| 8 | /// \file |
||
| 9 | /// |
||
| 10 | /// This file defines a class for holding ownership of various simulated |
||
| 11 | /// hardware units. A Context also provides a utility routine for constructing |
||
| 12 | /// a default out-of-order pipeline with fetch, dispatch, execute, and retire |
||
| 13 | /// stages. |
||
| 14 | /// |
||
| 15 | //===----------------------------------------------------------------------===// |
||
| 16 | |||
| 17 | #ifndef LLVM_MCA_CONTEXT_H |
||
| 18 | #define LLVM_MCA_CONTEXT_H |
||
| 19 | |||
| 20 | #include "llvm/MC/MCRegisterInfo.h" |
||
| 21 | #include "llvm/MC/MCSubtargetInfo.h" |
||
| 22 | #include "llvm/MCA/CustomBehaviour.h" |
||
| 23 | #include "llvm/MCA/HardwareUnits/HardwareUnit.h" |
||
| 24 | #include "llvm/MCA/Pipeline.h" |
||
| 25 | #include "llvm/MCA/SourceMgr.h" |
||
| 26 | #include <memory> |
||
| 27 | |||
| 28 | namespace llvm { |
||
| 29 | namespace mca { |
||
| 30 | |||
| 31 | /// This is a convenience struct to hold the parameters necessary for creating |
||
| 32 | /// the pre-built "default" out-of-order pipeline. |
||
| 33 | struct PipelineOptions { |
||
| 34 | PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, |
||
| 35 | unsigned LQS, unsigned SQS, bool NoAlias, |
||
| 36 | bool ShouldEnableBottleneckAnalysis = false) |
||
| 37 | : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr), |
||
| 38 | DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), |
||
| 39 | StoreQueueSize(SQS), AssumeNoAlias(NoAlias), |
||
| 40 | EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {} |
||
| 41 | unsigned MicroOpQueueSize; |
||
| 42 | unsigned DecodersThroughput; // Instructions per cycle. |
||
| 43 | unsigned DispatchWidth; |
||
| 44 | unsigned RegisterFileSize; |
||
| 45 | unsigned LoadQueueSize; |
||
| 46 | unsigned StoreQueueSize; |
||
| 47 | bool AssumeNoAlias; |
||
| 48 | bool EnableBottleneckAnalysis; |
||
| 49 | }; |
||
| 50 | |||
| 51 | class Context { |
||
| 52 | SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware; |
||
| 53 | const MCRegisterInfo &MRI; |
||
| 54 | const MCSubtargetInfo &STI; |
||
| 55 | |||
| 56 | public: |
||
| 57 | Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {} |
||
| 58 | Context(const Context &C) = delete; |
||
| 59 | Context &operator=(const Context &C) = delete; |
||
| 60 | |||
| 61 | const MCRegisterInfo &getMCRegisterInfo() const { return MRI; } |
||
| 62 | const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; } |
||
| 63 | |||
| 64 | void addHardwareUnit(std::unique_ptr<HardwareUnit> H) { |
||
| 65 | Hardware.push_back(std::move(H)); |
||
| 66 | } |
||
| 67 | |||
| 68 | /// Construct a basic pipeline for simulating an out-of-order pipeline. |
||
| 69 | /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages. |
||
| 70 | std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts, |
||
| 71 | SourceMgr &SrcMgr, |
||
| 72 | CustomBehaviour &CB); |
||
| 73 | |||
| 74 | /// Construct a basic pipeline for simulating an in-order pipeline. |
||
| 75 | /// This pipeline consists of Fetch, InOrderIssue, and Retire stages. |
||
| 76 | std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts, |
||
| 77 | SourceMgr &SrcMgr, |
||
| 78 | CustomBehaviour &CB); |
||
| 79 | }; |
||
| 80 | |||
| 81 | } // namespace mca |
||
| 82 | } // namespace llvm |
||
| 83 | #endif // LLVM_MCA_CONTEXT_H |