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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===// |
| 2 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 3 | // See https://llvm.org/LICENSE.txt for license information. |
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| 4 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 5 | // |
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| 6 | //===----------------------------------------------------------------------===// |
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| 7 | // |
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| 8 | // This file defines all of the Hexagon-specific intrinsics. |
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| 9 | // |
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| 10 | //===----------------------------------------------------------------------===// |
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| 11 | |||
| 12 | //===----------------------------------------------------------------------===// |
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| 13 | // Definitions for all Hexagon intrinsics. |
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| 14 | // |
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| 15 | // All Hexagon intrinsics start with "llvm.hexagon.". |
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| 16 | let TargetPrefix = "hexagon" in { |
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| 17 | /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. |
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| 18 | class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, |
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| 19 | list<LLVMType> param_types, |
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| 20 | list<IntrinsicProperty> properties> |
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| 21 | : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>, |
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| 22 | DefaultAttrsIntrinsic<ret_types, param_types, properties>; |
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| 23 | |||
| 24 | /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon |
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| 25 | /// intrinsics. |
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| 26 | class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types, |
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| 27 | list<LLVMType> param_types, |
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| 28 | list<IntrinsicProperty> properties> |
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| 29 | : DefaultAttrsIntrinsic<ret_types, param_types, properties>; |
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| 30 | } |
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| 31 | |||
| 32 | class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix> |
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| 33 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 34 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, |
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| 35 | llvm_i32_ty], |
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| 36 | [IntrArgMemOnly]>; |
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| 37 | |||
| 38 | class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix> |
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| 39 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 40 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, |
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| 41 | llvm_i32_ty], |
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| 42 | [IntrWriteMem]>; |
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| 43 | |||
| 44 | class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix> |
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| 45 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 46 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, |
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| 47 | llvm_i32_ty], |
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| 48 | [IntrWriteMem]>; |
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| 49 | |||
| 50 | class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix> |
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| 51 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 52 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, |
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| 53 | llvm_i32_ty, llvm_i32_ty], |
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| 54 | [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>; |
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| 55 | |||
| 56 | class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix> |
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| 57 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 58 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, |
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| 59 | llvm_i32_ty, llvm_i32_ty], |
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| 60 | [IntrWriteMem, ImmArg<ArgIndex<3>>]>; |
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| 61 | |||
| 62 | class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix> |
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| 63 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 64 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, |
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| 65 | llvm_i32_ty, llvm_i32_ty], |
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| 66 | [IntrWriteMem, ImmArg<ArgIndex<3>>]>; |
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| 67 | |||
| 68 | // |
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| 69 | // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4) |
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| 70 | // |
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| 71 | def int_hexagon_circ_ldd : |
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| 72 | Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">; |
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| 73 | // |
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| 74 | // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4) |
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| 75 | // |
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| 76 | def int_hexagon_circ_ldw : |
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| 77 | Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">; |
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| 78 | // |
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| 79 | // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4) |
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| 80 | // |
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| 81 | def int_hexagon_circ_ldh : |
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| 82 | Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">; |
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| 83 | // |
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| 84 | // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4) |
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| 85 | // |
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| 86 | def int_hexagon_circ_lduh : |
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| 87 | Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">; |
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| 88 | // |
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| 89 | // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4) |
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| 90 | // |
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| 91 | def int_hexagon_circ_ldb : |
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| 92 | Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">; |
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| 93 | // |
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| 94 | // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4) |
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| 95 | // |
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| 96 | def int_hexagon_circ_ldub : |
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| 97 | Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">; |
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| 98 | |||
| 99 | // |
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| 100 | // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4) |
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| 101 | // |
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| 102 | def int_hexagon_circ_std : |
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| 103 | Hexagon_mem_memdisisi_Intrinsic<"circ_std">; |
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| 104 | // |
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| 105 | // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4) |
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| 106 | // |
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| 107 | def int_hexagon_circ_stw : |
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| 108 | Hexagon_mem_memsisisi_Intrinsic<"circ_stw">; |
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| 109 | // |
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| 110 | // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4) |
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| 111 | // |
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| 112 | def int_hexagon_circ_sth : |
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| 113 | Hexagon_mem_memsisisi_Intrinsic<"circ_sth">; |
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| 114 | // |
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| 115 | // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4) |
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| 116 | // |
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| 117 | def int_hexagon_circ_sthhi : |
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| 118 | Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">; |
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| 119 | // |
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| 120 | // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4) |
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| 121 | // |
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| 122 | def int_hexagon_circ_stb : |
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| 123 | Hexagon_mem_memsisisi_Intrinsic<"circ_stb">; |
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| 124 | |||
| 125 | def int_hexagon_prefetch : |
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| 126 | Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>; |
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| 127 | |||
| 128 | def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>; |
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| 129 | def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>; |
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| 130 | |||
| 131 | // Mark locked loads as read/write to prevent any accidental reordering. |
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| 132 | // These don't use Hexagon_Intrinsic, because they are not nosync, and as such |
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| 133 | // cannot use default attributes. |
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| 134 | let TargetPrefix = "hexagon" in { |
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| 135 | def int_hexagon_L2_loadw_locked : |
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| 136 | ClangBuiltin<"__builtin_HEXAGON_L2_loadw_locked">, |
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| 137 | Intrinsic<[llvm_i32_ty], [llvm_ptr32_ty], |
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| 138 | [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; |
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| 139 | def int_hexagon_L4_loadd_locked : |
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| 140 | ClangBuiltin<"__builtin__HEXAGON_L4_loadd_locked">, |
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| 141 | Intrinsic<[llvm_i64_ty], [llvm_ptr64_ty], |
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| 142 | [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; |
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| 143 | |||
| 144 | def int_hexagon_S2_storew_locked : |
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| 145 | ClangBuiltin<"__builtin_HEXAGON_S2_storew_locked">, |
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| 146 | Intrinsic<[llvm_i32_ty], |
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| 147 | [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; |
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| 148 | def int_hexagon_S4_stored_locked : |
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| 149 | ClangBuiltin<"__builtin_HEXAGON_S4_stored_locked">, |
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| 150 | Intrinsic<[llvm_i32_ty], |
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| 151 | [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; |
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| 152 | } |
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| 153 | |||
| 154 | def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy", |
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| 155 | [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], |
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| 156 | [IntrArgMemOnly, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>]>; |
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| 157 | |||
| 158 | def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset", |
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| 159 | [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], |
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| 160 | [IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; |
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| 161 | |||
| 162 | multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { |
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| 163 | def NAME#_pci : Hexagon_NonGCC_Intrinsic< |
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| 164 | [ElTy, llvm_ptr_ty], |
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| 165 | [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], |
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| 166 | [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; |
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| 167 | def NAME#_pcr : Hexagon_NonGCC_Intrinsic< |
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| 168 | [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], |
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| 169 | [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; |
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| 170 | } |
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| 171 | |||
| 172 | defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; |
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| 173 | defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; |
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| 174 | defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; |
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| 175 | defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; |
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| 176 | defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; |
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| 177 | defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; |
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| 178 | |||
| 179 | multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { |
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| 180 | def NAME#_pci : Hexagon_NonGCC_Intrinsic< |
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| 181 | [llvm_ptr_ty], |
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| 182 | [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], |
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| 183 | [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; |
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| 184 | def NAME#_pcr : Hexagon_NonGCC_Intrinsic< |
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| 185 | [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], |
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| 186 | [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; |
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| 187 | } |
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| 188 | |||
| 189 | defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; |
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| 190 | defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; |
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| 191 | defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; |
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| 192 | defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; |
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| 193 | defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; |
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| 194 | |||
| 195 | // The front-end emits the intrinsic call with only two arguments. The third |
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| 196 | // argument from the builtin is already used by front-end to write to memory |
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| 197 | // by generating a store. |
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| 198 | class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> |
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| 199 | : Hexagon_NonGCC_Intrinsic< |
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| 200 | [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], |
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| 201 | [IntrReadMem]>; |
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| 202 | |||
| 203 | def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; |
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| 204 | def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; |
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| 205 | def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; |
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| 206 | def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; |
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| 207 | def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; |
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| 208 | def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; |
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| 209 | |||
| 210 | def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; |
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| 211 | def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; |
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| 212 | def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; |
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| 213 | def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; |
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| 214 | def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; |
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| 215 | |||
| 216 | // tag : V6_vrmpybub_rtt |
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| 217 | class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix> |
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| 218 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 219 | [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], |
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| 220 | [IntrNoMem]>; |
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| 221 | |||
| 222 | // tag : V6_vrmpybub_rtt_128B |
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| 223 | class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix> |
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| 224 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 225 | [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], |
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| 226 | [IntrNoMem]>; |
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| 227 | |||
| 228 | // tag : V6_vrmpybub_rtt_acc |
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| 229 | class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix> |
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| 230 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 231 | [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], |
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| 232 | [IntrNoMem]>; |
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| 233 | |||
| 234 | // tag : V6_vrmpybub_rtt_acc_128B |
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| 235 | class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix> |
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| 236 | : Hexagon_Intrinsic<GCCIntSuffix, |
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| 237 | [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], |
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| 238 | [IntrNoMem]>; |
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| 239 | |||
| 240 | def int_hexagon_V6_vrmpybub_rtt : |
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| 241 | Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; |
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| 242 | |||
| 243 | def int_hexagon_V6_vrmpybub_rtt_128B : |
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| 244 | Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; |
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| 245 | |||
| 246 | def int_hexagon_V6_vrmpybub_rtt_acc : |
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| 247 | Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; |
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| 248 | |||
| 249 | def int_hexagon_V6_vrmpybub_rtt_acc_128B : |
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| 250 | Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; |
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| 251 | |||
| 252 | def int_hexagon_V6_vrmpyub_rtt : |
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| 253 | Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; |
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| 254 | |||
| 255 | def int_hexagon_V6_vrmpyub_rtt_128B : |
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| 256 | Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; |
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| 257 | |||
| 258 | def int_hexagon_V6_vrmpyub_rtt_acc : |
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| 259 | Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; |
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| 260 | |||
| 261 | def int_hexagon_V6_vrmpyub_rtt_acc_128B : |
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| 262 | Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; |
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| 263 | |||
| 264 | // HVX conditional loads/stores |
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| 265 | |||
| 266 | class Hexagon_pred_vload_imm<LLVMType ValTy> |
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| 267 | : Hexagon_NonGCC_Intrinsic< |
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| 268 | [ValTy], |
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| 269 | [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty], |
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| 270 | [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, |
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| 271 | ImmArg<ArgIndex<2>>]>; |
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| 272 | |||
| 273 | class Hexagon_pred_vload_imm_64B: Hexagon_pred_vload_imm<llvm_v16i32_ty>; |
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| 274 | class Hexagon_pred_vload_imm_128B: Hexagon_pred_vload_imm<llvm_v32i32_ty>; |
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| 275 | |||
| 276 | def int_hexagon_V6_vL32b_pred_ai: Hexagon_pred_vload_imm_64B; |
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| 277 | def int_hexagon_V6_vL32b_npred_ai: Hexagon_pred_vload_imm_64B; |
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| 278 | def int_hexagon_V6_vL32b_nt_pred_ai: Hexagon_pred_vload_imm_64B; |
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| 279 | def int_hexagon_V6_vL32b_nt_npred_ai: Hexagon_pred_vload_imm_64B; |
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| 280 | def int_hexagon_V6_vL32b_pred_ai_128B: Hexagon_pred_vload_imm_128B; |
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| 281 | def int_hexagon_V6_vL32b_npred_ai_128B: Hexagon_pred_vload_imm_128B; |
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| 282 | def int_hexagon_V6_vL32b_nt_pred_ai_128B: Hexagon_pred_vload_imm_128B; |
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| 283 | def int_hexagon_V6_vL32b_nt_npred_ai_128B: Hexagon_pred_vload_imm_128B; |
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| 284 | |||
| 285 | class Hexagom_pred_vload_upd<LLVMType ValTy, bit TakesImm> |
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| 286 | : Hexagon_NonGCC_Intrinsic< |
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| 287 | [ValTy, LLVMPointerType<ValTy>], |
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| 288 | [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty], |
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| 289 | !if(TakesImm, |
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| 290 | [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, |
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| 291 | ImmArg<ArgIndex<2>>], |
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| 292 | [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; |
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| 293 | |||
| 294 | class Hexagom_pred_vload_upd_64B<bit TakesImm> |
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| 295 | : Hexagom_pred_vload_upd<llvm_v16i32_ty, TakesImm>; |
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| 296 | class Hexagom_pred_vload_upd_128B<bit TakesImm> |
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| 297 | : Hexagom_pred_vload_upd<llvm_v32i32_ty, TakesImm>; |
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| 298 | |||
| 299 | def int_hexagon_V6_vL32b_pred_pi: Hexagom_pred_vload_upd_64B<1>; |
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| 300 | def int_hexagon_V6_vL32b_npred_pi: Hexagom_pred_vload_upd_64B<1>; |
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| 301 | def int_hexagon_V6_vL32b_nt_pred_pi: Hexagom_pred_vload_upd_64B<1>; |
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| 302 | def int_hexagon_V6_vL32b_nt_npred_pi: Hexagom_pred_vload_upd_64B<1>; |
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| 303 | def int_hexagon_V6_vL32b_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; |
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| 304 | def int_hexagon_V6_vL32b_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; |
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| 305 | def int_hexagon_V6_vL32b_nt_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; |
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| 306 | def int_hexagon_V6_vL32b_nt_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; |
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| 307 | |||
| 308 | def int_hexagon_V6_vL32b_pred_ppu: Hexagom_pred_vload_upd_64B<0>; |
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| 309 | def int_hexagon_V6_vL32b_npred_ppu: Hexagom_pred_vload_upd_64B<0>; |
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| 310 | def int_hexagon_V6_vL32b_nt_pred_ppu: Hexagom_pred_vload_upd_64B<0>; |
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| 311 | def int_hexagon_V6_vL32b_nt_npred_ppu: Hexagom_pred_vload_upd_64B<0>; |
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| 312 | def int_hexagon_V6_vL32b_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; |
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| 313 | def int_hexagon_V6_vL32b_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; |
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| 314 | def int_hexagon_V6_vL32b_nt_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; |
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| 315 | def int_hexagon_V6_vL32b_nt_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; |
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| 316 | |||
| 317 | |||
| 318 | class Hexagon_pred_vstore_imm<LLVMType ValTy> |
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| 319 | : Hexagon_NonGCC_Intrinsic< |
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| 320 | [], |
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| 321 | [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy], |
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| 322 | [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, |
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| 323 | ImmArg<ArgIndex<2>>]>; |
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| 324 | |||
| 325 | class Hexagon_pred_vstore_imm_64B: Hexagon_pred_vstore_imm<llvm_v16i32_ty>; |
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| 326 | class Hexagon_pred_vstore_imm_128B: Hexagon_pred_vstore_imm<llvm_v32i32_ty>; |
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| 327 | |||
| 328 | def int_hexagon_V6_vS32b_pred_ai: Hexagon_pred_vstore_imm_64B; |
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| 329 | def int_hexagon_V6_vS32b_npred_ai: Hexagon_pred_vstore_imm_64B; |
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| 330 | def int_hexagon_V6_vS32Ub_pred_ai: Hexagon_pred_vstore_imm_64B; |
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| 331 | def int_hexagon_V6_vS32Ub_npred_ai: Hexagon_pred_vstore_imm_64B; |
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| 332 | def int_hexagon_V6_vS32b_nt_pred_ai: Hexagon_pred_vstore_imm_64B; |
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| 333 | def int_hexagon_V6_vS32b_nt_npred_ai: Hexagon_pred_vstore_imm_64B; |
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| 334 | def int_hexagon_V6_vS32b_pred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 335 | def int_hexagon_V6_vS32b_npred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 336 | def int_hexagon_V6_vS32Ub_pred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 337 | def int_hexagon_V6_vS32Ub_npred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 338 | def int_hexagon_V6_vS32b_nt_pred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 339 | def int_hexagon_V6_vS32b_nt_npred_ai_128B: Hexagon_pred_vstore_imm_128B; |
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| 340 | |||
| 341 | class Hexagon_pred_vstore_upd<LLVMType ValTy, bit TakesImm> |
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| 342 | : Hexagon_NonGCC_Intrinsic< |
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| 343 | [LLVMPointerType<ValTy>], |
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| 344 | [llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy], |
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| 345 | !if(TakesImm, |
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| 346 | [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, |
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| 347 | ImmArg<ArgIndex<2>>], |
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| 348 | [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; |
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| 349 | |||
| 350 | class Hexagon_pred_vstore_upd_64B<bit TakesImm> |
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| 351 | : Hexagon_pred_vstore_upd<llvm_v16i32_ty, TakesImm>; |
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| 352 | class Hexagon_pred_vstore_upd_128B<bit TakesImm> |
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| 353 | : Hexagon_pred_vstore_upd<llvm_v32i32_ty, TakesImm>; |
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| 354 | |||
| 355 | def int_hexagon_V6_vS32b_pred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 356 | def int_hexagon_V6_vS32b_npred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 357 | def int_hexagon_V6_vS32Ub_pred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 358 | def int_hexagon_V6_vS32Ub_npred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 359 | def int_hexagon_V6_vS32b_nt_pred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 360 | def int_hexagon_V6_vS32b_nt_npred_pi: Hexagon_pred_vstore_upd_64B<1>; |
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| 361 | def int_hexagon_V6_vS32b_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 362 | def int_hexagon_V6_vS32b_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 363 | def int_hexagon_V6_vS32Ub_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 364 | def int_hexagon_V6_vS32Ub_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 365 | def int_hexagon_V6_vS32b_nt_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 366 | def int_hexagon_V6_vS32b_nt_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; |
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| 367 | |||
| 368 | def int_hexagon_V6_vS32b_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 369 | def int_hexagon_V6_vS32b_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 370 | def int_hexagon_V6_vS32Ub_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 371 | def int_hexagon_V6_vS32Ub_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 372 | def int_hexagon_V6_vS32b_nt_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 373 | def int_hexagon_V6_vS32b_nt_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; |
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| 374 | def int_hexagon_V6_vS32b_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 375 | def int_hexagon_V6_vS32b_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 376 | def int_hexagon_V6_vS32Ub_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 377 | def int_hexagon_V6_vS32Ub_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 378 | def int_hexagon_V6_vS32b_nt_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 379 | def int_hexagon_V6_vS32b_nt_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; |
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| 380 | |||
| 381 | |||
| 382 | // HVX Vector predicate casts. |
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| 383 | // These intrinsics do not emit (nor do they correspond to) any instructions, |
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| 384 | // they are no-ops. |
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| 385 | |||
| 386 | def int_hexagon_V6_pred_typecast : |
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| 387 | Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; |
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| 388 | |||
| 389 | def int_hexagon_V6_pred_typecast_128B : |
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| 390 | Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; |
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| 391 | |||
| 392 | // HVX full-precision multiplication. |
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| 393 | // V6_vmpyss_parts(Vu,Vv) = (MulHS(Vu,Vv), Mul(Vu,Vv)) |
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| 394 | // V6_vmpyuu_parts(Vu,Vv) = (MulHU(Vu,Vv), Mul(Vu,Vv)) |
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| 395 | // V6_vmpyus_parts(Vu,Vv) = (MulHUS(Vu,Vv), Mul(Vu,Vv)) |
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| 396 | // |
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| 397 | // Both, the (purportedly) 64b and the _128B versions are exactly equivalent |
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| 398 | // regardless of the HVX mode, they are both defined for consistency. |
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| 399 | // The purpose of these intrinsics is to have a uniform way of multiplying two |
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| 400 | // integer vectors in the LLVM IR. Many HVX multiply operations interleave |
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| 401 | // the even-odd results, except for 32x32 multiplications. Also, different |
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| 402 | // HVX versions have different instructions that can be used, so defer the |
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| 403 | // instruction choice to the isel. |
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| 404 | class Hexagon_vv_vv_pure: |
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| 405 | Hexagon_NonGCC_Intrinsic< |
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| 406 | [llvm_anyvector_ty, LLVMMatchType<0>], |
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| 407 | [LLVMMatchType<0>, LLVMMatchType<0>], |
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| 408 | [IntrNoMem]>; |
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| 409 | |||
| 410 | def int_hexagon_V6_vmpyss_parts: Hexagon_vv_vv_pure; |
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| 411 | def int_hexagon_V6_vmpyss_parts_128B: Hexagon_vv_vv_pure; |
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| 412 | def int_hexagon_V6_vmpyuu_parts: Hexagon_vv_vv_pure; |
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| 413 | def int_hexagon_V6_vmpyuu_parts_128B: Hexagon_vv_vv_pure; |
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| 414 | def int_hexagon_V6_vmpyus_parts: Hexagon_vv_vv_pure; |
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| 415 | def int_hexagon_V6_vmpyus_parts_128B: Hexagon_vv_vv_pure; |
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| 416 | |||
| 417 | |||
| 418 | // Masked vector stores |
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| 419 | // |
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| 420 | // These are all deprecated, the intrinsics matching instruction names |
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| 421 | // should be used instead, e.g. int_hexagon_V6_vS32b_qpred_ai, etc. |
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| 422 | |||
| 423 | class Hexagon_custom_vms_Intrinsic |
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| 424 | : Hexagon_NonGCC_Intrinsic< |
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| 425 | [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], [IntrWriteMem]>; |
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| 426 | |||
| 427 | class Hexagon_custom_vms_Intrinsic_128B |
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| 428 | : Hexagon_NonGCC_Intrinsic< |
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| 429 | [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], [IntrWriteMem]>; |
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| 430 | |||
| 431 | def int_hexagon_V6_vmaskedstoreq: Hexagon_custom_vms_Intrinsic; |
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| 432 | def int_hexagon_V6_vmaskedstorenq: Hexagon_custom_vms_Intrinsic; |
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| 433 | def int_hexagon_V6_vmaskedstorentq: Hexagon_custom_vms_Intrinsic; |
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| 434 | def int_hexagon_V6_vmaskedstorentnq: Hexagon_custom_vms_Intrinsic; |
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| 435 | |||
| 436 | def int_hexagon_V6_vmaskedstoreq_128B: Hexagon_custom_vms_Intrinsic_128B; |
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| 437 | def int_hexagon_V6_vmaskedstorenq_128B: Hexagon_custom_vms_Intrinsic_128B; |
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| 438 | def int_hexagon_V6_vmaskedstorentq_128B: Hexagon_custom_vms_Intrinsic_128B; |
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| 439 | def int_hexagon_V6_vmaskedstorentnq_128B: Hexagon_custom_vms_Intrinsic_128B; |
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| 440 | |||
| 441 | |||
| 442 | // Intrinsic for instrumentation based profiling using a custom handler. The |
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| 443 | // name of the handler is passed as the first operand to the intrinsic. The |
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| 444 | // handler can take only one int32 input which is passed as the second |
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| 445 | // operand to the intrinsic. |
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| 446 | def int_hexagon_instrprof_custom |
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| 447 | : Hexagon_NonGCC_Intrinsic<[], |
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| 448 | [llvm_ptr_ty, llvm_i32_ty], |
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| 449 | [IntrInaccessibleMemOnly]>; |
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| 450 | |||
| 451 | |||
| 452 | include "llvm/IR/IntrinsicsHexagonDep.td" |