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//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

///

/// \file

/// This file describes how to lower LLVM code to machine code.  This has two

/// main components:

///

///  1. Which ValueTypes are natively supported by the target.

///  2. Which operations are supported for supported ValueTypes.

///  3. Cost thresholds for alternative implementations of certain operations.

///

/// In addition it has a few other components, like information about FP

/// immediates.

///

//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_TARGETLOWERING_H

#define LLVM_CODEGEN_TARGETLOWERING_H

#include "llvm/ADT/APInt.h"

#include "llvm/ADT/ArrayRef.h"

#include "llvm/ADT/DenseMap.h"

#include "llvm/ADT/SmallVector.h"

#include "llvm/ADT/StringRef.h"

#include "llvm/CodeGen/ComplexDeinterleavingPass.h"

#include "llvm/CodeGen/DAGCombine.h"

#include "llvm/CodeGen/ISDOpcodes.h"

#include "llvm/CodeGen/LowLevelType.h"

#include "llvm/CodeGen/RuntimeLibcalls.h"

#include "llvm/CodeGen/SelectionDAG.h"

#include "llvm/CodeGen/SelectionDAGNodes.h"

#include "llvm/CodeGen/TargetCallingConv.h"

#include "llvm/CodeGen/ValueTypes.h"

#include "llvm/IR/Attributes.h"

#include "llvm/IR/CallingConv.h"

#include "llvm/IR/DataLayout.h"

#include "llvm/IR/DerivedTypes.h"

#include "llvm/IR/Function.h"

#include "llvm/IR/InlineAsm.h"

#include "llvm/IR/Instruction.h"

#include "llvm/IR/Instructions.h"

#include "llvm/IR/Type.h"

#include "llvm/Support/Alignment.h"

#include "llvm/Support/AtomicOrdering.h"

#include "llvm/Support/Casting.h"

#include "llvm/Support/ErrorHandling.h"

#include "llvm/Support/MachineValueType.h"

#include <algorithm>

#include <cassert>

#include <climits>

#include <cstdint>

#include <iterator>

#include <map>

#include <string>

#include <utility>

#include <vector>

namespace llvm {

class AssumptionCache;

class CCState;

class CCValAssign;

class Constant;

class FastISel;

class FunctionLoweringInfo;

class GlobalValue;

class Loop;

class GISelKnownBits;

class IntrinsicInst;

class IRBuilderBase;

struct KnownBits;

class LegacyDivergenceAnalysis;

class LLVMContext;

class MachineBasicBlock;

class MachineFunction;

class MachineInstr;

class MachineJumpTableInfo;

class MachineLoop;

class MachineRegisterInfo;

class MCContext;

class MCExpr;

class Module;

class ProfileSummaryInfo;

class TargetLibraryInfo;

class TargetMachine;

class TargetRegisterClass;

class TargetRegisterInfo;

class TargetTransformInfo;

class Value;

namespace Sched {

enum Preference {

  None,        // No preference

  Source,      // Follow source order.

  RegPressure, // Scheduling for lowest register pressure.

  Hybrid,      // Scheduling for both latency and register pressure.

  ILP,         // Scheduling for ILP in low register pressure mode.

  VLIW,        // Scheduling for VLIW targets.

  Fast,        // Fast suboptimal list scheduling

  Linearize    // Linearize DAG, no scheduling

};

} // end namespace Sched

// MemOp models a memory operation, either memset or memcpy/memmove.

struct MemOp {

private:

  // Shared

  uint64_t Size;

  bool DstAlignCanChange; // true if destination alignment can satisfy any

                          // constraint.

  Align DstAlign;         // Specified alignment of the memory operation.

  bool AllowOverlap;

  // memset only

  bool IsMemset;   // If setthis memory operation is a memset.

  bool ZeroMemset; // If set clears out memory with zeros.

  // memcpy only

  bool MemcpyStrSrc; // Indicates whether the memcpy source is an in-register

                     // constant so it does not need to be loaded.

  Align SrcAlign;    // Inferred alignment of the source or default value if the

                     // memory operation does not need to load the value.

public:

  static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign,

                    Align SrcAlign, bool IsVolatile,

                    bool MemcpyStrSrc = false) {

    MemOp Op;

    Op.Size = Size;

    Op.DstAlignCanChange = DstAlignCanChange;

    Op.DstAlign = DstAlign;

    Op.AllowOverlap = !IsVolatile;

    Op.IsMemset = false;

    Op.ZeroMemset = false;

    Op.MemcpyStrSrc = MemcpyStrSrc;

    Op.SrcAlign = SrcAlign;

    return Op;

  }

  static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign,

                   bool IsZeroMemset, bool IsVolatile) {

    MemOp Op;

    Op.Size = Size;

    Op.DstAlignCanChange = DstAlignCanChange;

    Op.DstAlign = DstAlign;

    Op.AllowOverlap = !IsVolatile;

    Op.IsMemset = true;

    Op.ZeroMemset = IsZeroMemset;

    Op.MemcpyStrSrc = false;

    return Op;

  }

  uint64_t size() const { return Size; }

  Align getDstAlign() const {

    assert(!DstAlignCanChange);

    return DstAlign;

  }

  bool isFixedDstAlign() const { return !DstAlignCanChange; }

  bool allowOverlap() const { return AllowOverlap; }

  bool isMemset() const { return IsMemset; }

  bool isMemcpy() const { return !IsMemset; }

  bool isMemcpyWithFixedDstAlign() const {

    return isMemcpy() && !DstAlignCanChange;

  }

  bool isZeroMemset() const { return isMemset() && ZeroMemset; }

  bool isMemcpyStrSrc() const {

    assert(isMemcpy() && "Must be a memcpy");

    return MemcpyStrSrc;

  }

  Align getSrcAlign() const {

    assert(isMemcpy() && "Must be a memcpy");

    return SrcAlign;

  }

  bool isSrcAligned(Align AlignCheck) const {

    return isMemset() || llvm::isAligned(AlignCheck, SrcAlign.value());

  }

  bool isDstAligned(Align AlignCheck) const {

    return DstAlignCanChange || llvm::isAligned(AlignCheck, DstAlign.value());

  }

  bool isAligned(Align AlignCheck) const {

    return isSrcAligned(AlignCheck) && isDstAligned(AlignCheck);

  }

};

/// This base class for TargetLowering contains the SelectionDAG-independent

/// parts that can be used from the rest of CodeGen.

class TargetLoweringBase {

public:

  /// This enum indicates whether operations are valid for a target, and if not,

  /// what action should be used to make them valid.

  enum LegalizeAction : uint8_t {

    Legal,      // The target natively supports this operation.

    Promote,    // This operation should be executed in a larger type.

    Expand,     // Try to expand this to other ops, otherwise use a libcall.

    LibCall,    // Don't try to expand this to other ops, always use a libcall.

    Custom      // Use the LowerOperation hook to implement custom lowering.

  };

  /// This enum indicates whether a types are legal for a target, and if not,

  /// what action should be used to make them valid.

  enum LegalizeTypeAction : uint8_t {

    TypeLegal,           // The target natively supports this type.

    TypePromoteInteger,  // Replace this integer with a larger one.

    TypeExpandInteger,   // Split this integer into two of half the size.

    TypeSoftenFloat,     // Convert this float to a same size integer type.

    TypeExpandFloat,     // Split this float into two of half the size.

    TypeScalarizeVector, // Replace this one-element vector with its element.

    TypeSplitVector,     // Split this vector into two of half the size.

    TypeWidenVector,     // This vector should be widened into a larger vector.

    TypePromoteFloat,    // Replace this float with a larger one.

    TypeSoftPromoteHalf, // Soften half to i16 and use float to do arithmetic.

    TypeScalarizeScalableVector, // This action is explicitly left unimplemented.

                                 // While it is theoretically possible to

                                 // legalize operations on scalable types with a

                                 // loop that handles the vscale * #lanes of the

                                 // vector, this is non-trivial at SelectionDAG

                                 // level and these types are better to be

                                 // widened or promoted.

  };

  /// LegalizeKind holds the legalization kind that needs to happen to EVT

  /// in order to type-legalize it.

  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;

  /// Enum that describes how the target represents true/false values.

  enum BooleanContent {

    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.

    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.

    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.

  };

  /// Enum that describes what type of support for selects the target has.

  enum SelectSupportKind {

    ScalarValSelect,      // The target supports scalar selects (ex: cmov).

    ScalarCondVectorVal,  // The target supports selects with a scalar condition

                          // and vector values (ex: cmov).

    VectorMaskSelect      // The target supports vector selects with a vector

                          // mask (ex: x86 blends).

  };

  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded

  /// to, if at all. Exists because different targets have different levels of

  /// support for these atomic instructions, and also have different options

  /// w.r.t. what they should expand to.

  enum class AtomicExpansionKind {

    None,    // Don't expand the instruction.

    CastToInteger,    // Cast the atomic instruction to another type, e.g. from

                      // floating-point to integer type.

    LLSC,    // Expand the instruction into loadlinked/storeconditional; used

             // by ARM/AArch64.

    LLOnly,  // Expand the (load) instruction into just a load-linked, which has

             // greater atomic guarantees than a normal load.

    CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.

    MaskedIntrinsic,  // Use a target-specific intrinsic for the LL/SC loop.

    BitTestIntrinsic, // Use a target-specific intrinsic for special bit

                      // operations; used by X86.

    CmpArithIntrinsic,// Use a target-specific intrinsic for special compare

                      // operations; used by X86.

    Expand,           // Generic expansion in terms of other atomic operations.

    // Rewrite to a non-atomic form for use in a known non-preemptible

    // environment.

    NotAtomic

  };

  /// Enum that specifies when a multiplication should be expanded.

  enum class MulExpansionKind {

    Always,            // Always expand the instruction.

    OnlyLegalOrCustom, // Only expand when the resulting instructions are legal

                       // or custom.

  };

  /// Enum that specifies when a float negation is beneficial.

  enum class NegatibleCost {

    Cheaper = 0,    // Negated expression is cheaper.

    Neutral = 1,    // Negated expression has the same cost.

    Expensive = 2   // Negated expression is more expensive.

  };

  class ArgListEntry {

  public:

    Value *Val = nullptr;

    SDValue Node = SDValue();

    Type *Ty = nullptr;

    bool IsSExt : 1;

    bool IsZExt : 1;

    bool IsInReg : 1;

    bool IsSRet : 1;

    bool IsNest : 1;

    bool IsByVal : 1;

    bool IsByRef : 1;

    bool IsInAlloca : 1;

    bool IsPreallocated : 1;

    bool IsReturned : 1;

    bool IsSwiftSelf : 1;

    bool IsSwiftAsync : 1;

    bool IsSwiftError : 1;

    bool IsCFGuardTarget : 1;

    MaybeAlign Alignment = std::nullopt;

    Type *IndirectType = nullptr;

    ArgListEntry()

        : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),

          IsNest(false), IsByVal(false), IsByRef(false), IsInAlloca(false),

          IsPreallocated(false), IsReturned(false), IsSwiftSelf(false),

          IsSwiftAsync(false), IsSwiftError(false), IsCFGuardTarget(false) {}

    void setAttributes(const CallBase *Call, unsigned ArgIdx);

  };

  using ArgListTy = std::vector<ArgListEntry>;

  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,

                                     ArgListTy &Args) const {};

  static ISD::NodeType getExtendForContent(BooleanContent Content) {

    switch (Content) {

    case UndefinedBooleanContent:

      // Extend by adding rubbish bits.

      return ISD::ANY_EXTEND;

    case ZeroOrOneBooleanContent:

      // Extend by adding zero bits.

      return ISD::ZERO_EXTEND;

    case ZeroOrNegativeOneBooleanContent:

      // Extend by copying the sign bit.

      return ISD::SIGN_EXTEND;

    }

    llvm_unreachable("Invalid content kind");

  }

  explicit TargetLoweringBase(const TargetMachine &TM);

  TargetLoweringBase(const TargetLoweringBase &) = delete;

  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;

  virtual ~TargetLoweringBase() = default;

  /// Return true if the target support strict float operation

  bool isStrictFPEnabled() const {

    return IsStrictFPEnabled;

  }

protected:

  /// Initialize all of the actions to default values.

  void initActions();

public:

  const TargetMachine &getTargetMachine() const { return TM; }

  virtual bool useSoftFloat() const { return false; }

  /// Return the pointer type for the given address space, defaults to

  /// the pointer type from the data layout.

  /// FIXME: The default needs to be removed once all the code is updated.

  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {

    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));

  }

  /// Return the in-memory pointer type for the given address space, defaults to

  /// the pointer type from the data layout.  FIXME: The default needs to be

  /// removed once all the code is updated.

  virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {

    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));

  }

  /// Return the type for frame index, which is determined by

  /// the alloca address space specified through the data layout.

  MVT getFrameIndexTy(const DataLayout &DL) const {

    return getPointerTy(DL, DL.getAllocaAddrSpace());

  }

  /// Return the type for code pointers, which is determined by the program

  /// address space specified through the data layout.

  MVT getProgramPointerTy(const DataLayout &DL) const {

    return getPointerTy(DL, DL.getProgramAddressSpace());

  }

  /// Return the type for operands of fence.

  /// TODO: Let fence operands be of i32 type and remove this.

  virtual MVT getFenceOperandTy(const DataLayout &DL) const {

    return getPointerTy(DL);

  }

  /// Return the type to use for a scalar shift opcode, given the shifted amount

  /// type. Targets should return a legal type if the input type is legal.

  /// Targets can return a type that is too small if the input type is illegal.

  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;

  /// Returns the type for the shift amount of a shift opcode. For vectors,

  /// returns the input type. For scalars, behavior depends on \p LegalTypes. If

  /// \p LegalTypes is true, calls getScalarShiftAmountTy, otherwise uses

  /// pointer type. If getScalarShiftAmountTy or pointer type cannot represent

  /// all possible shift amounts, returns MVT::i32. In general, \p LegalTypes

  /// should be set to true for calls during type legalization and after type

  /// legalization has been completed.

  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,

                       bool LegalTypes = true) const;

  /// Return the preferred type to use for a shift opcode, given the shifted

  /// amount type is \p ShiftValueTy.

  LLVM_READONLY

  virtual LLT getPreferredShiftAmountTy(LLT ShiftValueTy) const {

    return ShiftValueTy;

  }

  /// Returns the type to be used for the index operand of:

  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,

  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

  virtual MVT getVectorIdxTy(const DataLayout &DL) const {

    return getPointerTy(DL);

  }

  /// Returns the type to be used for the EVL/AVL operand of VP nodes:

  /// ISD::VP_ADD, ISD::VP_SUB, etc. It must be a legal scalar integer type,

  /// and must be at least as large as i32. The EVL is implicitly zero-extended

  /// to any larger type.

  virtual MVT getVPExplicitVectorLengthTy() const { return MVT::i32; }

  /// This callback is used to inspect load/store instructions and add

  /// target-specific MachineMemOperand flags to them.  The default

  /// implementation does nothing.

  virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const {

    return MachineMemOperand::MONone;

  }

  MachineMemOperand::Flags

  getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL,

                         AssumptionCache *AC = nullptr,

                         const TargetLibraryInfo *LibInfo = nullptr) const;

  MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI,

                                                   const DataLayout &DL) const;

  MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI,

                                                    const DataLayout &DL) const;

  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {

    return true;

  }

  /// Return true if the @llvm.get.active.lane.mask intrinsic should be expanded

  /// using generic code in SelectionDAGBuilder.

  virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const {

    return true;

  }

  /// Return true if it is profitable to convert a select of FP constants into

  /// a constant pool load whose address depends on the select condition. The

  /// parameter may be used to differentiate a select with FP compare from

  /// integer compare.

  virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {

    return true;

  }

  /// Return true if multiple condition registers are available.

  bool hasMultipleConditionRegisters() const {

    return HasMultipleConditionRegisters;

  }

  /// Return true if the target has BitExtract instructions.

  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }

  /// Return the preferred vector type legalization action.

  virtual TargetLoweringBase::LegalizeTypeAction

  getPreferredVectorAction(MVT VT) const {

    // The default action for one element vectors is to scalarize

    if (VT.getVectorElementCount().isScalar())

      return TypeScalarizeVector;

    // The default action for an odd-width vector is to widen.

    if (!VT.isPow2VectorType())

      return TypeWidenVector;

    // The default action for other vectors is to promote

    return TypePromoteInteger;

  }

  // Return true if the half type should be passed around as i16, but promoted

  // to float around arithmetic. The default behavior is to pass around as

  // float and convert around loads/stores/bitcasts and other places where

  // the size matters.

  virtual bool softPromoteHalfType() const { return false; }

  // There are two general methods for expanding a BUILD_VECTOR node:

  //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle

  //     them together.

  //  2. Build the vector on the stack and then load it.

  // If this function returns true, then method (1) will be used, subject to

  // the constraint that all of the necessary shuffles are legal (as determined

  // by isShuffleMaskLegal). If this function returns false, then method (2) is

  // always used. The vector type, and the number of defined values, are

  // provided.

  virtual bool

  shouldExpandBuildVectorWithShuffles(EVT /* VT */,

                                      unsigned DefinedValues) const {

    return DefinedValues < 3;

  }

  /// Return true if integer divide is usually cheaper than a sequence of

  /// several shifts, adds, and multiplies for this target.

  /// The definition of "cheaper" may depend on whether we're optimizing

  /// for speed or for size.

  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }

  /// Return true if the target can handle a standalone remainder operation.

  virtual bool hasStandaloneRem(EVT VT) const {

    return true;

  }

  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {

    // Default behavior is to replace SQRT(X) with X*RSQRT(X).

    return false;

  }

  /// Reciprocal estimate status values used by the functions below.

  enum ReciprocalEstimate : int {

    Unspecified = -1,

    Disabled = 0,

    Enabled = 1

  };

  /// Return a ReciprocalEstimate enum value for a square root of the given type

  /// based on the function's attributes. If the operation is not overridden by

  /// the function's attributes, "Unspecified" is returned and target defaults

  /// are expected to be used for instruction selection.

  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;

  /// Return a ReciprocalEstimate enum value for a division of the given type

  /// based on the function's attributes. If the operation is not overridden by

  /// the function's attributes, "Unspecified" is returned and target defaults

  /// are expected to be used for instruction selection.

  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;

  /// Return the refinement step count for a square root of the given type based

  /// on the function's attributes. If the operation is not overridden by

  /// the function's attributes, "Unspecified" is returned and target defaults

  /// are expected to be used for instruction selection.

  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;

  /// Return the refinement step count for a division of the given type based

  /// on the function's attributes. If the operation is not overridden by

  /// the function's attributes, "Unspecified" is returned and target defaults

  /// are expected to be used for instruction selection.

  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;

  /// Returns true if target has indicated at least one type should be bypassed.

  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }

  /// Returns map of slow types for division or remainder with corresponding

  /// fast types

  const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {

    return BypassSlowDivWidths;

  }

  /// Return true only if vscale must be a power of two.

  virtual bool isVScaleKnownToBeAPowerOfTwo() const { return false; }

  /// Return true if Flow Control is an expensive operation that should be

  /// avoided.

  bool isJumpExpensive() const { return JumpIsExpensive; }

  /// Return true if selects are only cheaper than branches if the branch is

  /// unlikely to be predicted right.

  bool isPredictableSelectExpensive() const {

    return PredictableSelectIsExpensive;

  }

  virtual bool fallBackToDAGISel(const Instruction &Inst) const {

    return false;

  }

  /// Return true if the following transform is beneficial:

  /// fold (conv (load x)) -> (load (conv*)x)

  /// On architectures that don't natively support some vector loads

  /// efficiently, casting the load to a smaller vector of larger types and

  /// loading is more efficient, however, this can be undone by optimizations in

  /// dag combiner.

  virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,

                                       const SelectionDAG &DAG,

                                       const MachineMemOperand &MMO) const;

  /// Return true if the following transform is beneficial:

  /// (store (y (conv x)), y*)) -> (store x, (x*))

  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,

                                        const SelectionDAG &DAG,

                                        const MachineMemOperand &MMO) const {

    // Default to the same logic as loads.

    return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);

  }

  /// Return true if it is expected to be cheaper to do a store of a non-zero

  /// vector constant with the given size and type for the address space than to

  /// store the individual scalar element constants.

  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,

                                            unsigned NumElem,

                                            unsigned AddrSpace) const {

    return false;

  }

  /// Allow store merging for the specified type after legalization in addition

  /// to before legalization. This may transform stores that do not exist

  /// earlier (for example, stores created from intrinsics).

  virtual bool mergeStoresAfterLegalization(EVT MemVT) const {

    return true;

  }

  /// Returns if it's reasonable to merge stores to MemVT size.

  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,

                                const MachineFunction &MF) const {

    return true;

  }

  /// Return true if it is cheap to speculate a call to intrinsic cttz.

  virtual bool isCheapToSpeculateCttz(Type *Ty) const {

    return false;

  }

  /// Return true if it is cheap to speculate a call to intrinsic ctlz.

  virtual bool isCheapToSpeculateCtlz(Type *Ty) const {

    return false;

  }

  /// Return true if ctlz instruction is fast.

  virtual bool isCtlzFast() const {

    return false;

  }

  /// Return the maximum number of "x & (x - 1)" operations that can be done

  /// instead of deferring to a custom CTPOP.

  virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const {

    return 1;

  }

  /// Return true if instruction generated for equality comparison is folded

  /// with instruction generated for signed comparison.

  virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }

  /// Return true if the heuristic to prefer icmp eq zero should be used in code

  /// gen prepare.

  virtual bool preferZeroCompareBranch() const { return false; }

  /// Return true if it is safe to transform an integer-domain bitwise operation

  /// into the equivalent floating-point operation. This should be set to true

  /// if the target has IEEE-754-compliant fabs/fneg operations for the input

  /// type.

  virtual bool hasBitPreservingFPLogic(EVT VT) const {

    return false;

  }

  /// Return true if it is cheaper to split the store of a merged int val

  /// from a pair of smaller values into multiple stores.

  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {

    return false;

  }

  /// Return if the target supports combining a

  /// chain like:

  /// \code

  ///   %andResult = and %val1, #mask

  ///   %icmpResult = icmp %andResult, 0

  /// \endcode

  /// into a single machine instruction of a form like:

  /// \code

  ///   cc = test %register, #mask

  /// \endcode

  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {

    return false;

  }

  /// Use bitwise logic to make pairs of compares more efficient. For example:

  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0

  /// This should be true when it takes more than one instruction to lower

  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on

  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {

    return false;

  }

  /// Return the preferred operand type if the target has a quick way to compare

  /// integer values of the given size. Assume that any legal integer type can

  /// be compared efficiently. Targets may override this to allow illegal wide

  /// types to return a vector type if there is support to compare that type.

  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {

    MVT VT = MVT::getIntegerVT(NumBits);

    return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;

  }

  /// Return true if the target should transform:

  /// (X & Y) == Y ---> (~X & Y) == 0

  /// (X & Y) != Y ---> (~X & Y) != 0

  ///

  /// This may be profitable if the target has a bitwise and-not operation that

  /// sets comparison flags. A target may want to limit the transformation based

  /// on the type of Y or if Y is a constant.

  ///

  /// Note that the transform will not occur if Y is known to be a power-of-2

  /// because a mask and compare of a single bit can be handled by inverting the

  /// predicate, for example:

  /// (X & 8) == 8 ---> (X & 8) != 0

  virtual bool hasAndNotCompare(SDValue Y) const {

    return false;

  }

  /// Return true if the target has a bitwise and-not operation:

  /// X = ~A & B

  /// This can be used to simplify select or other instructions.

  virtual bool hasAndNot(SDValue X) const {

    // If the target has the more complex version of this operation, assume that

    // it has this operation too.

    return hasAndNotCompare(X);

  }

  /// Return true if the target has a bit-test instruction:

  ///   (X & (1 << Y)) ==/!= 0

  /// This knowledge can be used to prevent breaking the pattern,

  /// or creating it if it could be recognized.

  virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }

  /// There are two ways to clear extreme bits (either low or high):

  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)

  /// Shifts:  x >> y << y

  /// Return true if the variant with 2 variable shifts is preferred.

  /// Return false if there is no preference.

  virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const {

    // By default, let's assume that no one prefers shifts.

    return false;

  }

  /// Return true if it is profitable to fold a pair of shifts into a mask.

  /// This is usually true on most targets. But some targets, like Thumb1,

  /// have immediate shift instructions, but no immediate "and" instruction;

  /// this makes the fold unprofitable.

  virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,

                                                 CombineLevel Level) const {

    return true;

  }

  /// Should we tranform the IR-optimal check for whether given truncation

  /// down into KeptBits would be truncating or not:

  ///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)

  /// Into it's more traditional form:

  ///   ((%x << C) a>> C) dstcond %x

  /// Return true if we should transform.

  /// Return false if there is no preference.

  virtual bool shouldTransformSignedTruncationCheck(EVT XVT,

                                                    unsigned KeptBits) const {

    // By default, let's assume that no one prefers shifts.

    return false;

  }

  /// Given the pattern

  ///   (X & (C l>>/<< Y)) ==/!= 0

  /// return true if it should be transformed into:

  ///   ((X <</l>> Y) & C) ==/!= 0

  /// WARNING: if 'X' is a constant, the fold may deadlock!

  /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()

  ///        here because it can end up being not linked in.

  virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(

      SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,

      unsigned OldShiftOpcode, unsigned NewShiftOpcode,

      SelectionDAG &DAG) const {

    if (hasBitTest(X, Y)) {

      // One interesting pattern that we'd want to form is 'bit test':

      //   ((1 << Y) & C) ==/!= 0

      // But we also need to be careful not to try to reverse that fold.

      // Is this '1 << Y' ?

      if (OldShiftOpcode == ISD::SHL && CC->isOne())

        return false; // Keep the 'bit test' pattern.

      // Will it be '1 << Y' after the transform ?

      if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())

        return true; // Do form the 'bit test' pattern.

    }

    // If 'X' is a constant, and we transform, then we will immediately

    // try to undo the fold, thus causing endless combine loop.

    // So by default, let's assume everyone prefers the fold

    // iff 'X' is not a constant.

    return !XC;

  }

  /// These two forms are equivalent:

  ///   sub %y, (xor %x, -1)

  ///   add (add %x, 1), %y

  /// The variant with two add's is IR-canonical.

  /// Some targets may prefer one to the other.

  virtual bool preferIncOfAddToSubOfNot(EVT VT) const {

    // By default, let's assume that everyone prefers the form with two add's.

    return true;

  }

  // Return true if the target wants to transform Op(Splat(X)) -> Splat(Op(X))

  virtual bool preferScalarizeSplat(unsigned Opc) const { return true; }

  /// Return true if the target wants to use the optimization that

  /// turns ext(promotableInst1(...(promotableInstN(load)))) into

  /// promotedInst1(...(promotedInstN(ext(load)))).

  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }

  /// Return true if the target can combine store(extractelement VectorTy,

  /// Idx).

  /// \p Cost[out] gives the cost of that transformation when this is true.

  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,

                                         unsigned &Cost) const {

    return false;

  }

  /// Return true if inserting a scalar into a variable element of an undef

  /// vector is more efficiently handled by splatting the scalar instead.

  virtual bool shouldSplatInsEltVarIndex(EVT) const {

    return false;

  }

  /// Return true if target always benefits from combining into FMA for a

  /// given value type. This must typically return false on targets where FMA

  /// takes more cycles to execute than FADD.

  virtual bool enableAggressiveFMAFusion(EVT VT) const { return false; }

  /// Return true if target always benefits from combining into FMA for a

  /// given value type. This must typically return false on targets where FMA

  /// takes more cycles to execute than FADD.

  virtual bool enableAggressiveFMAFusion(LLT Ty) const { return false; }

  /// Return the ValueType of the result of SETCC operations.

  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,

                                 EVT VT) const;

  /// Return the ValueType for comparison libcalls. Comparison libcalls include

  /// floating point comparison calls, and Ordered/Unordered check calls on

  /// floating point numbers.

  virtual

  MVT::SimpleValueType getCmpLibcallReturnType() const;

  /// For targets without i1 registers, this gives the nature of the high-bits

  /// of boolean values held in types wider than i1.

  ///

  /// "Boolean values" are special true/false values produced by nodes like

  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.

  /// Not to be confused with general values promoted from i1.  Some cpus

  /// distinguish between vectors of boolean and scalars; the isVec parameter

  /// selects between the two kinds.  For example on X86 a scalar boolean should

  /// be zero extended from i1, while the elements of a vector of booleans

  /// should be sign extended from i1.

  ///

  /// Some cpus also treat floating point types the same way as they treat

  /// vectors instead of the way they treat scalars.

  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {

    if (isVec)

      return BooleanVectorContents;

    return isFloat ? BooleanFloatContents : BooleanContents;

  }

  BooleanContent getBooleanContents(EVT Type) const {

    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());

  }

  /// Promote the given target boolean to a target boolean of the given type.

  /// A target boolean is an integer value, not necessarily of type i1, the bits

  /// of which conform to getBooleanContents.

  ///

  /// ValVT is the type of values that produced the boolean.

  SDValue promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool,

                               EVT ValVT) const {

    SDLoc dl(Bool);

    EVT BoolVT =