Subversion Repositories QNX 8.QNX8 LLVM/Clang compiler suite

//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// This file describes the target machine instruction set to the code generator.

//

//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_TARGETINSTRINFO_H

#define LLVM_CODEGEN_TARGETINSTRINFO_H

#include "llvm/ADT/ArrayRef.h"

#include "llvm/ADT/DenseMap.h"

#include "llvm/ADT/DenseMapInfo.h"

#include "llvm/ADT/Uniformity.h"

#include "llvm/CodeGen/MIRFormatter.h"

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/CodeGen/MachineFunction.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"

#include "llvm/CodeGen/MachineOperand.h"

#include "llvm/CodeGen/MachineOutliner.h"

#include "llvm/CodeGen/RegisterClassInfo.h"

#include "llvm/CodeGen/VirtRegMap.h"

#include "llvm/MC/MCInstrInfo.h"

#include "llvm/Support/BranchProbability.h"

#include "llvm/Support/ErrorHandling.h"

#include <cassert>

#include <cstddef>

#include <cstdint>

#include <utility>

#include <vector>

namespace llvm {

class DFAPacketizer;

class InstrItineraryData;

class LiveIntervals;

class LiveVariables;

class MachineLoop;

class MachineMemOperand;

class MachineRegisterInfo;

class MCAsmInfo;

class MCInst;

struct MCSchedModel;

class Module;

class ScheduleDAG;

class ScheduleDAGMI;

class ScheduleHazardRecognizer;

class SDNode;

class SelectionDAG;

class SMSchedule;

class SwingSchedulerDAG;

class RegScavenger;

class TargetRegisterClass;

class TargetRegisterInfo;

class TargetSchedModel;

class TargetSubtargetInfo;

enum class MachineCombinerPattern;

template <class T> class SmallVectorImpl;

using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;

struct DestSourcePair {

  const MachineOperand *Destination;

  const MachineOperand *Source;

  DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)

      : Destination(&Dest), Source(&Src) {}

};

/// Used to describe a register and immediate addition.

struct RegImmPair {

  Register Reg;

  int64_t Imm;

  RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}

};

/// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.

/// It holds the register values, the scale value and the displacement.

struct ExtAddrMode {

  Register BaseReg;

  Register ScaledReg;

  int64_t Scale;

  int64_t Displacement;

};

//---------------------------------------------------------------------------

///

/// TargetInstrInfo - Interface to description of machine instruction set

///

class TargetInstrInfo : public MCInstrInfo {

public:

  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,

                  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)

      : CallFrameSetupOpcode(CFSetupOpcode),

        CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),

        ReturnOpcode(ReturnOpcode) {}

  TargetInstrInfo(const TargetInstrInfo &) = delete;

  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;

  virtual ~TargetInstrInfo();

  static bool isGenericOpcode(unsigned Opc) {

    return Opc <= TargetOpcode::GENERIC_OP_END;

  }

  static bool isGenericAtomicRMWOpcode(unsigned Opc) {

    return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&

           Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;

  }

  /// Given a machine instruction descriptor, returns the register

  /// class constraint for OpNum, or NULL.

  virtual

  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,

                                         const TargetRegisterInfo *TRI,

                                         const MachineFunction &MF) const;

  /// Return true if the instruction is trivially rematerializable, meaning it

  /// has no side effects and requires no operands that aren't always available.

  /// This means the only allowed uses are constants and unallocatable physical

  /// registers so that the instructions result is independent of the place

  /// in the function.

  bool isTriviallyReMaterializable(const MachineInstr &MI) const {

    return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||

           (MI.getDesc().isRematerializable() &&

            (isReallyTriviallyReMaterializable(MI) ||

             isReallyTriviallyReMaterializableGeneric(MI)));

  }

  /// Given \p MO is a PhysReg use return if it can be ignored for the purpose

  /// of instruction rematerialization or sinking.

  virtual bool isIgnorableUse(const MachineOperand &MO) const {

    return false;

  }

protected:

  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is

  /// set, this hook lets the target specify whether the instruction is actually

  /// trivially rematerializable, taking into consideration its operands. This

  /// predicate must return false if the instruction has any side effects other

  /// than producing a value, or if it requres any address registers that are

  /// not always available.

  /// Requirements must be check as stated in isTriviallyReMaterializable() .

  virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const {

    return false;

  }

  /// This method commutes the operands of the given machine instruction MI.

  /// The operands to be commuted are specified by their indices OpIdx1 and

  /// OpIdx2.

  ///

  /// If a target has any instructions that are commutable but require

  /// converting to different instructions or making non-trivial changes

  /// to commute them, this method can be overloaded to do that.

  /// The default implementation simply swaps the commutable operands.

  ///

  /// If NewMI is false, MI is modified in place and returned; otherwise, a

  /// new machine instruction is created and returned.

  ///

  /// Do not call this method for a non-commutable instruction.

  /// Even though the instruction is commutable, the method may still

  /// fail to commute the operands, null pointer is returned in such cases.

  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,

                                               unsigned OpIdx1,

                                               unsigned OpIdx2) const;

  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable

  /// operand indices to (ResultIdx1, ResultIdx2).

  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be

  /// predefined to some indices or be undefined (designated by the special

  /// value 'CommuteAnyOperandIndex').

  /// The predefined result indices cannot be re-defined.

  /// The function returns true iff after the result pair redefinition

  /// the fixed result pair is equal to or equivalent to the source pair of

  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that

  /// the pairs (x,y) and (y,x) are equivalent.

  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,

                                   unsigned CommutableOpIdx1,

                                   unsigned CommutableOpIdx2);

private:

  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is

  /// set and the target hook isReallyTriviallyReMaterializable returns false,

  /// this function does target-independent tests to determine if the

  /// instruction is really trivially rematerializable.

  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI) const;

public:

  /// These methods return the opcode of the frame setup/destroy instructions

  /// if they exist (-1 otherwise).  Some targets use pseudo instructions in

  /// order to abstract away the difference between operating with a frame

  /// pointer and operating without, through the use of these two instructions.

  ///

  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }

  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }

  /// Returns true if the argument is a frame pseudo instruction.

  bool isFrameInstr(const MachineInstr &I) const {

    return I.getOpcode() == getCallFrameSetupOpcode() ||

           I.getOpcode() == getCallFrameDestroyOpcode();

  }

  /// Returns true if the argument is a frame setup pseudo instruction.

  bool isFrameSetup(const MachineInstr &I) const {

    return I.getOpcode() == getCallFrameSetupOpcode();

  }

  /// Returns size of the frame associated with the given frame instruction.

  /// For frame setup instruction this is frame that is set up space set up

  /// after the instruction. For frame destroy instruction this is the frame

  /// freed by the caller.

  /// Note, in some cases a call frame (or a part of it) may be prepared prior

  /// to the frame setup instruction. It occurs in the calls that involve

  /// inalloca arguments. This function reports only the size of the frame part

  /// that is set up between the frame setup and destroy pseudo instructions.

  int64_t getFrameSize(const MachineInstr &I) const {

    assert(isFrameInstr(I) && "Not a frame instruction");

    assert(I.getOperand(0).getImm() >= 0);

    return I.getOperand(0).getImm();

  }

  /// Returns the total frame size, which is made up of the space set up inside

  /// the pair of frame start-stop instructions and the space that is set up

  /// prior to the pair.

  int64_t getFrameTotalSize(const MachineInstr &I) const {

    if (isFrameSetup(I)) {

      assert(I.getOperand(1).getImm() >= 0 &&

             "Frame size must not be negative");

      return getFrameSize(I) + I.getOperand(1).getImm();

    }

    return getFrameSize(I);

  }

  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }

  unsigned getReturnOpcode() const { return ReturnOpcode; }

  /// Returns the actual stack pointer adjustment made by an instruction

  /// as part of a call sequence. By default, only call frame setup/destroy

  /// instructions adjust the stack, but targets may want to override this

  /// to enable more fine-grained adjustment, or adjust by a different value.

  virtual int getSPAdjust(const MachineInstr &MI) const;

  /// Return true if the instruction is a "coalescable" extension instruction.

  /// That is, it's like a copy where it's legal for the source to overlap the

  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's

  /// expected the pre-extension value is available as a subreg of the result

  /// register. This also returns the sub-register index in SubIdx.

  virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,

                                     Register &DstReg, unsigned &SubIdx) const {

    return false;

  }

  /// If the specified machine instruction is a direct

  /// load from a stack slot, return the virtual or physical register number of

  /// the destination along with the FrameIndex of the loaded stack slot.  If

  /// not, return 0.  This predicate must return 0 if the instruction has

  /// any side effects other than loading from the stack slot.

  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,

                                       int &FrameIndex) const {

    return 0;

  }

  /// Optional extension of isLoadFromStackSlot that returns the number of

  /// bytes loaded from the stack. This must be implemented if a backend

  /// supports partial stack slot spills/loads to further disambiguate

  /// what the load does.

  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,

                                       int &FrameIndex,

                                       unsigned &MemBytes) const {

    MemBytes = 0;

    return isLoadFromStackSlot(MI, FrameIndex);

  }

  /// Check for post-frame ptr elimination stack locations as well.

  /// This uses a heuristic so it isn't reliable for correctness.

  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,

                                             int &FrameIndex) const {

    return 0;

  }

  /// If the specified machine instruction has a load from a stack slot,

  /// return true along with the FrameIndices of the loaded stack slot and the

  /// machine mem operands containing the reference.

  /// If not, return false.  Unlike isLoadFromStackSlot, this returns true for

  /// any instructions that loads from the stack.  This is just a hint, as some

  /// cases may be missed.

  virtual bool hasLoadFromStackSlot(

      const MachineInstr &MI,

      SmallVectorImpl<const MachineMemOperand *> &Accesses) const;

  /// If the specified machine instruction is a direct

  /// store to a stack slot, return the virtual or physical register number of

  /// the source reg along with the FrameIndex of the loaded stack slot.  If

  /// not, return 0.  This predicate must return 0 if the instruction has

  /// any side effects other than storing to the stack slot.

  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,

                                      int &FrameIndex) const {

    return 0;

  }

  /// Optional extension of isStoreToStackSlot that returns the number of

  /// bytes stored to the stack. This must be implemented if a backend

  /// supports partial stack slot spills/loads to further disambiguate

  /// what the store does.

  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,

                                      int &FrameIndex,

                                      unsigned &MemBytes) const {

    MemBytes = 0;

    return isStoreToStackSlot(MI, FrameIndex);

  }

  /// Check for post-frame ptr elimination stack locations as well.

  /// This uses a heuristic, so it isn't reliable for correctness.

  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,

                                            int &FrameIndex) const {

    return 0;

  }

  /// If the specified machine instruction has a store to a stack slot,

  /// return true along with the FrameIndices of the loaded stack slot and the

  /// machine mem operands containing the reference.

  /// If not, return false.  Unlike isStoreToStackSlot,

  /// this returns true for any instructions that stores to the

  /// stack.  This is just a hint, as some cases may be missed.

  virtual bool hasStoreToStackSlot(

      const MachineInstr &MI,

      SmallVectorImpl<const MachineMemOperand *> &Accesses) const;

  /// Return true if the specified machine instruction

  /// is a copy of one stack slot to another and has no other effect.

  /// Provide the identity of the two frame indices.

  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,

                               int &SrcFrameIndex) const {

    return false;

  }

  /// Compute the size in bytes and offset within a stack slot of a spilled

  /// register or subregister.

  ///

  /// \param [out] Size in bytes of the spilled value.

  /// \param [out] Offset in bytes within the stack slot.

  /// \returns true if both Size and Offset are successfully computed.

  ///

  /// Not all subregisters have computable spill slots. For example,

  /// subregisters registers may not be byte-sized, and a pair of discontiguous

  /// subregisters has no single offset.

  ///

  /// Targets with nontrivial bigendian implementations may need to override

  /// this, particularly to support spilled vector registers.

  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,

                                 unsigned &Size, unsigned &Offset,

                                 const MachineFunction &MF) const;

  /// Return true if the given instruction is terminator that is unspillable,

  /// according to isUnspillableTerminatorImpl.

  bool isUnspillableTerminator(const MachineInstr *MI) const {

    return MI->isTerminator() && isUnspillableTerminatorImpl(MI);

  }

  /// Returns the size in bytes of the specified MachineInstr, or ~0U

  /// when this function is not implemented by a target.

  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {

    return ~0U;

  }

  /// Return true if the instruction is as cheap as a move instruction.

  ///

  /// Targets for different archs need to override this, and different

  /// micro-architectures can also be finely tuned inside.

  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {

    return MI.isAsCheapAsAMove();

  }

  /// Return true if the instruction should be sunk by MachineSink.

  ///

  /// MachineSink determines on its own whether the instruction is safe to sink;

  /// this gives the target a hook to override the default behavior with regards

  /// to which instructions should be sunk.

  virtual bool shouldSink(const MachineInstr &MI) const { return true; }

  /// Return false if the instruction should not be hoisted by MachineLICM.

  ///

  /// MachineLICM determines on its own whether the instruction is safe to

  /// hoist; this gives the target a hook to extend this assessment and prevent

  /// an instruction being hoisted from a given loop for target specific

  /// reasons.

  virtual bool shouldHoist(const MachineInstr &MI,

                           const MachineLoop *FromLoop) const {

    return true;

  }

  /// Re-issue the specified 'original' instruction at the

  /// specific location targeting a new destination register.

  /// The register in Orig->getOperand(0).getReg() will be substituted by

  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with

  /// SubIdx.

  virtual void reMaterialize(MachineBasicBlock &MBB,

                             MachineBasicBlock::iterator MI, Register DestReg,

                             unsigned SubIdx, const MachineInstr &Orig,

                             const TargetRegisterInfo &TRI) const;

  /// Clones instruction or the whole instruction bundle \p Orig and

  /// insert into \p MBB before \p InsertBefore. The target may update operands

  /// that are required to be unique.

  ///

  /// \p Orig must not return true for MachineInstr::isNotDuplicable().

  virtual MachineInstr &duplicate(MachineBasicBlock &MBB,

                                  MachineBasicBlock::iterator InsertBefore,

                                  const MachineInstr &Orig) const;

  /// This method must be implemented by targets that

  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target

  /// may be able to convert a two-address instruction into one or more true

  /// three-address instructions on demand.  This allows the X86 target (for

  /// example) to convert ADD and SHL instructions into LEA instructions if they

  /// would require register copies due to two-addressness.

  ///

  /// This method returns a null pointer if the transformation cannot be

  /// performed, otherwise it returns the last new instruction.

  ///

  /// If \p LIS is not nullptr, the LiveIntervals info should be updated for

  /// replacing \p MI with new instructions, even though this function does not

  /// remove MI.

  virtual MachineInstr *convertToThreeAddress(MachineInstr &MI,

                                              LiveVariables *LV,

                                              LiveIntervals *LIS) const {

    return nullptr;

  }

  // This constant can be used as an input value of operand index passed to

  // the method findCommutedOpIndices() to tell the method that the

  // corresponding operand index is not pre-defined and that the method

  // can pick any commutable operand.

  static const unsigned CommuteAnyOperandIndex = ~0U;

  /// This method commutes the operands of the given machine instruction MI.

  ///

  /// The operands to be commuted are specified by their indices OpIdx1 and

  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value

  /// 'CommuteAnyOperandIndex', which means that the method is free to choose

  /// any arbitrarily chosen commutable operand. If both arguments are set to

  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable

  /// operands; then commutes them if such operands could be found.

  ///

  /// If NewMI is false, MI is modified in place and returned; otherwise, a

  /// new machine instruction is created and returned.

  ///

  /// Do not call this method for a non-commutable instruction or

  /// for non-commuable operands.

  /// Even though the instruction is commutable, the method may still

  /// fail to commute the operands, null pointer is returned in such cases.

  MachineInstr *

  commuteInstruction(MachineInstr &MI, bool NewMI = false,

                     unsigned OpIdx1 = CommuteAnyOperandIndex,

                     unsigned OpIdx2 = CommuteAnyOperandIndex) const;

  /// Returns true iff the routine could find two commutable operands in the

  /// given machine instruction.

  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.

  /// If any of the INPUT values is set to the special value

  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable

  /// operand, then returns its index in the corresponding argument.

  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method

  /// looks for 2 commutable operands.

  /// If INPUT values refer to some operands of MI, then the method simply

  /// returns true if the corresponding operands are commutable and returns

  /// false otherwise.

  ///

  /// For example, calling this method this way:

  ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;

  ///     findCommutedOpIndices(MI, Op1, Op2);

  /// can be interpreted as a query asking to find an operand that would be

  /// commutable with the operand#1.

  virtual bool findCommutedOpIndices(const MachineInstr &MI,

                                     unsigned &SrcOpIdx1,

                                     unsigned &SrcOpIdx2) const;

  /// Returns true if the target has a preference on the operands order of

  /// the given machine instruction. And specify if \p Commute is required to

  /// get the desired operands order.

  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {

    return false;

  }

  /// A pair composed of a register and a sub-register index.

  /// Used to give some type checking when modeling Reg:SubReg.

  struct RegSubRegPair {

    Register Reg;

    unsigned SubReg;

    RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)

        : Reg(Reg), SubReg(SubReg) {}

    bool operator==(const RegSubRegPair& P) const {

      return Reg == P.Reg && SubReg == P.SubReg;

    }

    bool operator!=(const RegSubRegPair& P) const {

      return !(*this == P);

    }

  };

  /// A pair composed of a pair of a register and a sub-register index,

  /// and another sub-register index.

  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.

  struct RegSubRegPairAndIdx : RegSubRegPair {

    unsigned SubIdx;

    RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,

                        unsigned SubIdx = 0)

        : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}

  };

  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI

  /// and \p DefIdx.

  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of

  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef

  /// flag are not added to this list.

  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce

  /// two elements:

  /// - %1:sub1, sub0

  /// - %2<:0>, sub1

  ///

  /// \returns true if it is possible to build such an input sequence

  /// with the pair \p MI, \p DefIdx. False otherwise.

  ///

  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().

  ///

  /// \note The generic implementation does not provide any support for

  /// MI.isRegSequenceLike(). In other words, one has to override

  /// getRegSequenceLikeInputs for target specific instructions.

  bool

  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,

                       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;

  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI

  /// and \p DefIdx.

  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.

  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

  /// - %1:sub1, sub0

  ///

  /// \returns true if it is possible to build such an input sequence

  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.

  /// False otherwise.

  ///

  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().

  ///

  /// \note The generic implementation does not provide any support for

  /// MI.isExtractSubregLike(). In other words, one has to override

  /// getExtractSubregLikeInputs for target specific instructions.

  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,

                              RegSubRegPairAndIdx &InputReg) const;

  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI

  /// and \p DefIdx.

  /// \p [out] BaseReg and \p [out] InsertedReg contain

  /// the equivalent inputs of INSERT_SUBREG.

  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

  /// - BaseReg: %0:sub0

  /// - InsertedReg: %1:sub1, sub3

  ///

  /// \returns true if it is possible to build such an input sequence

  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.

  /// False otherwise.

  ///

  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().

  ///

  /// \note The generic implementation does not provide any support for

  /// MI.isInsertSubregLike(). In other words, one has to override

  /// getInsertSubregLikeInputs for target specific instructions.

  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,

                             RegSubRegPair &BaseReg,

                             RegSubRegPairAndIdx &InsertedReg) const;

  /// Return true if two machine instructions would produce identical values.

  /// By default, this is only true when the two instructions

  /// are deemed identical except for defs. If this function is called when the

  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for

  /// aggressive checks.

  virtual bool produceSameValue(const MachineInstr &MI0,

                                const MachineInstr &MI1,

                                const MachineRegisterInfo *MRI = nullptr) const;

  /// \returns true if a branch from an instruction with opcode \p BranchOpc

  ///  bytes is capable of jumping to a position \p BrOffset bytes away.

  virtual bool isBranchOffsetInRange(unsigned BranchOpc,

                                     int64_t BrOffset) const {

    llvm_unreachable("target did not implement");

  }

  /// \returns The block that branch instruction \p MI jumps to.

  virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {

    llvm_unreachable("target did not implement");

  }

  /// Insert an unconditional indirect branch at the end of \p MBB to \p

  /// NewDestBB. Optionally, insert the clobbered register restoring in \p

  /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to

  /// the offset of the position to insert the new branch.

  virtual void insertIndirectBranch(MachineBasicBlock &MBB,

                                    MachineBasicBlock &NewDestBB,

                                    MachineBasicBlock &RestoreBB,

                                    const DebugLoc &DL, int64_t BrOffset = 0,

                                    RegScavenger *RS = nullptr) const {

    llvm_unreachable("target did not implement");

  }

  /// Analyze the branching code at the end of MBB, returning

  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't

  /// implemented for a target).  Upon success, this returns false and returns

  /// with the following information in various cases:

  ///

  /// 1. If this block ends with no branches (it just falls through to its succ)

  ///    just return false, leaving TBB/FBB null.

  /// 2. If this block ends with only an unconditional branch, it sets TBB to be

  ///    the destination block.

  /// 3. If this block ends with a conditional branch and it falls through to a

  ///    successor block, it sets TBB to be the branch destination block and a

  ///    list of operands that evaluate the condition. These operands can be

  ///    passed to other TargetInstrInfo methods to create new branches.

  /// 4. If this block ends with a conditional branch followed by an

  ///    unconditional branch, it returns the 'true' destination in TBB, the

  ///    'false' destination in FBB, and a list of operands that evaluate the

  ///    condition.  These operands can be passed to other TargetInstrInfo

  ///    methods to create new branches.

  ///

  /// Note that removeBranch and insertBranch must be implemented to support

  /// cases where this method returns success.

  ///

  /// If AllowModify is true, then this routine is allowed to modify the basic

  /// block (e.g. delete instructions after the unconditional branch).

  ///

  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid

  /// before calling this function.

  virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,

                             MachineBasicBlock *&FBB,

                             SmallVectorImpl<MachineOperand> &Cond,

                             bool AllowModify = false) const {

    return true;

  }

  /// Represents a predicate at the MachineFunction level.  The control flow a

  /// MachineBranchPredicate represents is:

  ///

  ///  Reg = LHS `Predicate` RHS         == ConditionDef

  ///  if Reg then goto TrueDest else goto FalseDest

  ///

  struct MachineBranchPredicate {

    enum ComparePredicate {

      PRED_EQ,     // True if two values are equal

      PRED_NE,     // True if two values are not equal

      PRED_INVALID // Sentinel value

    };

    ComparePredicate Predicate = PRED_INVALID;

    MachineOperand LHS = MachineOperand::CreateImm(0);

    MachineOperand RHS = MachineOperand::CreateImm(0);

    MachineBasicBlock *TrueDest = nullptr;

    MachineBasicBlock *FalseDest = nullptr;

    MachineInstr *ConditionDef = nullptr;

    /// SingleUseCondition is true if ConditionDef is dead except for the

    /// branch(es) at the end of the basic block.

    ///

    bool SingleUseCondition = false;

    explicit MachineBranchPredicate() = default;

  };

  /// Analyze the branching code at the end of MBB and parse it into the

  /// MachineBranchPredicate structure if possible.  Returns false on success

  /// and true on failure.

  ///

  /// If AllowModify is true, then this routine is allowed to modify the basic

  /// block (e.g. delete instructions after the unconditional branch).

  ///

  virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,

                                      MachineBranchPredicate &MBP,

                                      bool AllowModify = false) const {

    return true;

  }

  /// Remove the branching code at the end of the specific MBB.

  /// This is only invoked in cases where analyzeBranch returns success. It

  /// returns the number of instructions that were removed.

  /// If \p BytesRemoved is non-null, report the change in code size from the

  /// removed instructions.

  virtual unsigned removeBranch(MachineBasicBlock &MBB,

                                int *BytesRemoved = nullptr) const {

    llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");

  }

  /// Insert branch code into the end of the specified MachineBasicBlock. The

  /// operands to this method are the same as those returned by analyzeBranch.

  /// This is only invoked in cases where analyzeBranch returns success. It

  /// returns the number of instructions inserted. If \p BytesAdded is non-null,

  /// report the change in code size from the added instructions.

  ///

  /// It is also invoked by tail merging to add unconditional branches in

  /// cases where analyzeBranch doesn't apply because there was no original

  /// branch to analyze.  At least this much must be implemented, else tail

  /// merging needs to be disabled.

  ///

  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid

  /// before calling this function.

  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,

                                MachineBasicBlock *FBB,

                                ArrayRef<MachineOperand> Cond,

                                const DebugLoc &DL,

                                int *BytesAdded = nullptr) const {

    llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");

  }

  unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,

                                     MachineBasicBlock *DestBB,

                                     const DebugLoc &DL,

                                     int *BytesAdded = nullptr) const {

    return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,

                        BytesAdded);

  }

  /// Object returned by analyzeLoopForPipelining. Allows software pipelining

  /// implementations to query attributes of the loop being pipelined and to

  /// apply target-specific updates to the loop once pipelining is complete.

  class PipelinerLoopInfo {

  public:

    virtual ~PipelinerLoopInfo();

    /// Return true if the given instruction should not be pipelined and should

    /// be ignored. An example could be a loop comparison, or induction variable

    /// update with no users being pipelined.

    virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;

    /// Return true if the proposed schedule should used.  Otherwise return

    /// false to not pipeline the loop. This function should be used to ensure

    /// that pipelined loops meet target-specific quality heuristics.

    virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS) {

      return true;

    }

    /// Create a condition to determine if the trip count of the loop is greater

    /// than TC, where TC is always one more than for the previous prologue or

    /// 0 if this is being called for the outermost prologue.

    ///

    /// If the trip count is statically known to be greater than TC, return

    /// true. If the trip count is statically known to be not greater than TC,

    /// return false. Otherwise return nullopt and fill out Cond with the test

    /// condition.

    ///

    /// Note: This hook is guaranteed to be called from the innermost to the

    /// outermost prologue of the loop being software pipelined.

    virtual std::optional<bool>

    createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,

                                    SmallVectorImpl<MachineOperand> &Cond) = 0;

    /// Modify the loop such that the trip count is

    /// OriginalTC + TripCountAdjust.

    virtual void adjustTripCount(int TripCountAdjust) = 0;

    /// Called when the loop's preheader has been modified to NewPreheader.

    virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;

    /// Called when the loop is being removed. Any instructions in the preheader

    /// should be removed.

    ///

    /// Once this function is called, no other functions on this object are

    /// valid; the loop has been removed.

    virtual void disposed() = 0;

  };

  /// Analyze loop L, which must be a single-basic-block loop, and if the

  /// conditions can be understood enough produce a PipelinerLoopInfo object.

  virtual std::unique_ptr<PipelinerLoopInfo>

  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {

    return nullptr;

  }

  /// Analyze the loop code, return true if it cannot be understood. Upon

  /// success, this function returns false and returns information about the

  /// induction variable and compare instruction used at the end.

  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,

                           MachineInstr *&CmpInst) const {

    return true;

  }

  /// Generate code to reduce the loop iteration by one and check if the loop

  /// is finished.  Return the value/register of the new loop count.  We need

  /// this function when peeling off one or more iterations of a loop. This

  /// function assumes the nth iteration is peeled first.

  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,

                                   MachineBasicBlock &PreHeader,

                                   MachineInstr *IndVar, MachineInstr &Cmp,

                                   SmallVectorImpl<MachineOperand> &Cond,

                                   SmallVectorImpl<MachineInstr *> &PrevInsts,

                                   unsigned Iter, unsigned MaxIter) const {

    llvm_unreachable("Target didn't implement ReduceLoopCount");

  }

  /// Delete the instruction OldInst and everything after it, replacing it with

  /// an unconditional branch to NewDest. This is used by the tail merging pass.

  virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,

                                       MachineBasicBlock *NewDest) const;

  /// Return true if it's legal to split the given basic

  /// block at the specified instruction (i.e. instruction would be the start

  /// of a new basic block).

  virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,

                                   MachineBasicBlock::iterator MBBI) const {

    return true;

  }

  /// Return true if it's profitable to predicate

  /// instructions with accumulated instruction latency of "NumCycles"

  /// of the specified basic block, where the probability of the instructions

  /// being executed is given by Probability, and Confidence is a measure

  /// of our confidence that it will be properly predicted.

  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,

                                   unsigned ExtraPredCycles,

                                   BranchProbability Probability) const {

    return false;

  }

  /// Second variant of isProfitableToIfCvt. This one

  /// checks for the case where two basic blocks from true and false path

  /// of a if-then-else (diamond) are predicated on mutually exclusive

  /// predicates, where the probability of the true path being taken is given

  /// by Probability, and Confidence is a measure of our confidence that it

  /// will be properly predicted.

  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,

                                   unsigned ExtraTCycles,

                                   MachineBasicBlock &FMBB, unsigned NumFCycles,

                                   unsigned ExtraFCycles,

                                   BranchProbability Probability) const {

    return false;

  }

  /// Return true if it's profitable for if-converter to duplicate instructions

  /// of specified accumulated instruction latencies in the specified MBB to

  /// enable if-conversion.

  /// The probability of the instructions being executed is given by

  /// Probability, and Confidence is a measure of our confidence that it

  /// will be properly predicted.

  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,

                                         unsigned NumCycles,

                                         BranchProbability Probability) const {

    return false;

  }

  /// Return the increase in code size needed to predicate a contiguous run of

  /// NumInsts instructions.

  virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,

                                                    unsigned NumInsts) const {

    return 0;

  }

  /// Return an estimate for the code size reduction (in bytes) which will be

  /// caused by removing the given branch instruction during if-conversion.

  virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {

    return getInstSizeInBytes(MI);

  }

  /// Return true if it's profitable to unpredicate

  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually

  /// exclusive predicates.

  /// e.g.

  ///   subeq  r0, r1, #1

  ///   addne  r0, r1, #1

  /// =>

  ///   sub    r0, r1, #1

  ///   addne  r0, r1, #1

  ///

  /// This may be profitable is conditional instructions are always executed.

  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,

                                         MachineBasicBlock &FMBB) const {