Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | //==-- llvm/CodeGen/RegisterBank.h - Register Bank ---------------*- C++ -*-==// |
| 2 | // |
||
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
||
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
||
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
||
| 6 | // |
||
| 7 | //===----------------------------------------------------------------------===// |
||
| 8 | // |
||
| 9 | /// \file This file declares the API of register banks. |
||
| 10 | // |
||
| 11 | //===----------------------------------------------------------------------===// |
||
| 12 | |||
| 13 | #ifndef LLVM_CODEGEN_REGISTERBANK_H |
||
| 14 | #define LLVM_CODEGEN_REGISTERBANK_H |
||
| 15 | |||
| 16 | #include "llvm/ADT/BitVector.h" |
||
| 17 | |||
| 18 | namespace llvm { |
||
| 19 | // Forward declarations. |
||
| 20 | class RegisterBankInfo; |
||
| 21 | class raw_ostream; |
||
| 22 | class TargetRegisterClass; |
||
| 23 | class TargetRegisterInfo; |
||
| 24 | |||
| 25 | /// This class implements the register bank concept. |
||
| 26 | /// Two instances of RegisterBank must have different ID. |
||
| 27 | /// This property is enforced by the RegisterBankInfo class. |
||
| 28 | class RegisterBank { |
||
| 29 | private: |
||
| 30 | unsigned ID; |
||
| 31 | const char *Name; |
||
| 32 | unsigned Size; |
||
| 33 | BitVector ContainedRegClasses; |
||
| 34 | |||
| 35 | /// Sentinel value used to recognize register bank not properly |
||
| 36 | /// initialized yet. |
||
| 37 | static const unsigned InvalidID; |
||
| 38 | |||
| 39 | /// Only the RegisterBankInfo can initialize RegisterBank properly. |
||
| 40 | friend RegisterBankInfo; |
||
| 41 | |||
| 42 | public: |
||
| 43 | RegisterBank(unsigned ID, const char *Name, unsigned Size, |
||
| 44 | const uint32_t *CoveredClasses, unsigned NumRegClasses); |
||
| 45 | |||
| 46 | /// Get the identifier of this register bank. |
||
| 47 | unsigned getID() const { return ID; } |
||
| 48 | |||
| 49 | /// Get a user friendly name of this register bank. |
||
| 50 | /// Should be used only for debugging purposes. |
||
| 51 | const char *getName() const { return Name; } |
||
| 52 | |||
| 53 | /// Get the maximal size in bits that fits in this register bank. |
||
| 54 | unsigned getSize() const { return Size; } |
||
| 55 | |||
| 56 | /// Check whether this instance is ready to be used. |
||
| 57 | bool isValid() const; |
||
| 58 | |||
| 59 | /// Check if this register bank is valid. In other words, |
||
| 60 | /// if it has been properly constructed. |
||
| 61 | /// |
||
| 62 | /// \note This method does not check anything when assertions are disabled. |
||
| 63 | /// |
||
| 64 | /// \return True is the check was successful. |
||
| 65 | bool verify(const TargetRegisterInfo &TRI) const; |
||
| 66 | |||
| 67 | /// Check whether this register bank covers \p RC. |
||
| 68 | /// In other words, check if this register bank fully covers |
||
| 69 | /// the registers that \p RC contains. |
||
| 70 | /// \pre isValid() |
||
| 71 | bool covers(const TargetRegisterClass &RC) const; |
||
| 72 | |||
| 73 | /// Check whether \p OtherRB is the same as this. |
||
| 74 | bool operator==(const RegisterBank &OtherRB) const; |
||
| 75 | bool operator!=(const RegisterBank &OtherRB) const { |
||
| 76 | return !this->operator==(OtherRB); |
||
| 77 | } |
||
| 78 | |||
| 79 | /// Dump the register mask on dbgs() stream. |
||
| 80 | /// The dump is verbose. |
||
| 81 | void dump(const TargetRegisterInfo *TRI = nullptr) const; |
||
| 82 | |||
| 83 | /// Print the register mask on OS. |
||
| 84 | /// If IsForDebug is false, then only the name of the register bank |
||
| 85 | /// is printed. Otherwise, all the fields are printing. |
||
| 86 | /// TRI is then used to print the name of the register classes that |
||
| 87 | /// this register bank covers. |
||
| 88 | void print(raw_ostream &OS, bool IsForDebug = false, |
||
| 89 | const TargetRegisterInfo *TRI = nullptr) const; |
||
| 90 | }; |
||
| 91 | |||
| 92 | inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) { |
||
| 93 | RegBank.print(OS); |
||
| 94 | return OS; |
||
| 95 | } |
||
| 96 | } // End namespace llvm. |
||
| 97 | |||
| 98 | #endif |