Subversion Repositories QNX 8.QNX8 LLVM/Clang compiler suite

//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

/// \file

/// This file declares the MachineIRBuilder class.

/// This is a helper class to build MachineInstr.

//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H

#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H

#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/CodeGen/MachineInstrBuilder.h"

#include "llvm/CodeGen/MachineRegisterInfo.h"

#include "llvm/CodeGen/TargetOpcodes.h"

#include "llvm/IR/DebugLoc.h"

#include "llvm/IR/Module.h"

namespace llvm {

// Forward declarations.

class APInt;

class BlockAddress;

class Constant;

class ConstantFP;

class ConstantInt;

class DataLayout;

class GISelCSEInfo;

class GlobalValue;

class TargetRegisterClass;

class MachineFunction;

class MachineInstr;

class TargetInstrInfo;

class GISelChangeObserver;

/// Class which stores all the state required in a MachineIRBuilder.

/// Since MachineIRBuilders will only store state in this object, it allows

/// to transfer BuilderState between different kinds of MachineIRBuilders.

struct MachineIRBuilderState {

  /// MachineFunction under construction.

  MachineFunction *MF = nullptr;

  /// Information used to access the description of the opcodes.

  const TargetInstrInfo *TII = nullptr;

  /// Information used to verify types are consistent and to create virtual registers.

  MachineRegisterInfo *MRI = nullptr;

  /// Debug location to be set to any instruction we create.

  DebugLoc DL;

  /// PC sections metadata to be set to any instruction we create.

  MDNode *PCSections = nullptr;

  /// \name Fields describing the insertion point.

  /// @{

  MachineBasicBlock *MBB = nullptr;

  MachineBasicBlock::iterator II;

  /// @}

  GISelChangeObserver *Observer = nullptr;

  GISelCSEInfo *CSEInfo = nullptr;

};

class DstOp {

  union {

    LLT LLTTy;

    Register Reg;

    const TargetRegisterClass *RC;

  };

public:

  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };

  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}

  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}

  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}

  DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}

  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}

  void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {

    switch (Ty) {

    case DstType::Ty_Reg:

      MIB.addDef(Reg);

      break;

    case DstType::Ty_LLT:

      MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));

      break;

    case DstType::Ty_RC:

      MIB.addDef(MRI.createVirtualRegister(RC));

      break;

    }

  }

  LLT getLLTTy(const MachineRegisterInfo &MRI) const {

    switch (Ty) {

    case DstType::Ty_RC:

      return LLT{};

    case DstType::Ty_LLT:

      return LLTTy;

    case DstType::Ty_Reg:

      return MRI.getType(Reg);

    }

    llvm_unreachable("Unrecognised DstOp::DstType enum");

  }

  Register getReg() const {

    assert(Ty == DstType::Ty_Reg && "Not a register");

    return Reg;

  }

  const TargetRegisterClass *getRegClass() const {

    switch (Ty) {

    case DstType::Ty_RC:

      return RC;

    default:

      llvm_unreachable("Not a RC Operand");

    }

  }

  DstType getDstOpKind() const { return Ty; }

private:

  DstType Ty;

};

class SrcOp {

  union {

    MachineInstrBuilder SrcMIB;

    Register Reg;

    CmpInst::Predicate Pred;

    int64_t Imm;

  };

public:

  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };

  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}

  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}

  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}

  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}

  /// Use of registers held in unsigned integer variables (or more rarely signed

  /// integers) is no longer permitted to avoid ambiguity with upcoming support

  /// for immediates.

  SrcOp(unsigned) = delete;

  SrcOp(int) = delete;

  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}

  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}

  void addSrcToMIB(MachineInstrBuilder &MIB) const {

    switch (Ty) {

    case SrcType::Ty_Predicate:

      MIB.addPredicate(Pred);

      break;

    case SrcType::Ty_Reg:

      MIB.addUse(Reg);

      break;

    case SrcType::Ty_MIB:

      MIB.addUse(SrcMIB->getOperand(0).getReg());

      break;

    case SrcType::Ty_Imm:

      MIB.addImm(Imm);

      break;

    }

  }

  LLT getLLTTy(const MachineRegisterInfo &MRI) const {

    switch (Ty) {

    case SrcType::Ty_Predicate:

    case SrcType::Ty_Imm:

      llvm_unreachable("Not a register operand");

    case SrcType::Ty_Reg:

      return MRI.getType(Reg);

    case SrcType::Ty_MIB:

      return MRI.getType(SrcMIB->getOperand(0).getReg());

    }

    llvm_unreachable("Unrecognised SrcOp::SrcType enum");

  }

  Register getReg() const {

    switch (Ty) {

    case SrcType::Ty_Predicate:

    case SrcType::Ty_Imm:

      llvm_unreachable("Not a register operand");

    case SrcType::Ty_Reg:

      return Reg;

    case SrcType::Ty_MIB:

      return SrcMIB->getOperand(0).getReg();

    }

    llvm_unreachable("Unrecognised SrcOp::SrcType enum");

  }

  CmpInst::Predicate getPredicate() const {

    switch (Ty) {

    case SrcType::Ty_Predicate:

      return Pred;

    default:

      llvm_unreachable("Not a register operand");

    }

  }

  int64_t getImm() const {

    switch (Ty) {

    case SrcType::Ty_Imm:

      return Imm;

    default:

      llvm_unreachable("Not an immediate");

    }

  }

  SrcType getSrcOpKind() const { return Ty; }

private:

  SrcType Ty;

};

/// Helper class to build MachineInstr.

/// It keeps internally the insertion point and debug location for all

/// the new instructions we want to create.

/// This information can be modified via the related setters.

class MachineIRBuilder {

  MachineIRBuilderState State;

  unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;

protected:

  void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);

  void validateUnaryOp(const LLT Res, const LLT Op0);

  void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);

  void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);

  void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,

                        const LLT Op1Ty);

  void recordInsertion(MachineInstr *InsertedInstr) const {

    if (State.Observer)

      State.Observer->createdInstr(*InsertedInstr);

  }

public:

  /// Some constructors for easy use.

  MachineIRBuilder() = default;

  MachineIRBuilder(MachineFunction &MF) { setMF(MF); }

  MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) {

    setMF(*MBB.getParent());

    setInsertPt(MBB, InsPt);

  }

  MachineIRBuilder(MachineInstr &MI) :

    MachineIRBuilder(*MI.getParent(), MI.getIterator()) {

    setInstr(MI);

    setDebugLoc(MI.getDebugLoc());

  }

  MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) :

    MachineIRBuilder(MI) {

    setChangeObserver(Observer);

  }

  virtual ~MachineIRBuilder() = default;

  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}

  const TargetInstrInfo &getTII() {

    assert(State.TII && "TargetInstrInfo is not set");

    return *State.TII;

  }

  /// Getter for the function we currently build.

  MachineFunction &getMF() {

    assert(State.MF && "MachineFunction is not set");

    return *State.MF;

  }

  const MachineFunction &getMF() const {

    assert(State.MF && "MachineFunction is not set");

    return *State.MF;

  }

  const DataLayout &getDataLayout() const {

    return getMF().getFunction().getParent()->getDataLayout();

  }

  /// Getter for DebugLoc

  const DebugLoc &getDL() { return State.DL; }

  /// Getter for MRI

  MachineRegisterInfo *getMRI() { return State.MRI; }

  const MachineRegisterInfo *getMRI() const { return State.MRI; }

  /// Getter for the State

  MachineIRBuilderState &getState() { return State; }

  /// Getter for the basic block we currently build.

  const MachineBasicBlock &getMBB() const {

    assert(State.MBB && "MachineBasicBlock is not set");

    return *State.MBB;

  }

  MachineBasicBlock &getMBB() {

    return const_cast<MachineBasicBlock &>(

        const_cast<const MachineIRBuilder *>(this)->getMBB());

  }

  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }

  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }

  /// Current insertion point for new instructions.

  MachineBasicBlock::iterator getInsertPt() { return State.II; }

  /// Set the insertion point before the specified position.

  /// \pre MBB must be in getMF().

  /// \pre II must be a valid iterator in MBB.

  void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) {

    assert(MBB.getParent() == &getMF() &&

           "Basic block is in a different function");

    State.MBB = &MBB;

    State.II = II;

  }

  /// @}

  void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }

  /// \name Setters for the insertion point.

  /// @{

  /// Set the MachineFunction where to build instructions.

  void setMF(MachineFunction &MF);

  /// Set the insertion point to the  end of \p MBB.

  /// \pre \p MBB must be contained by getMF().

  void setMBB(MachineBasicBlock &MBB) {

    State.MBB = &MBB;

    State.II = MBB.end();

    assert(&getMF() == MBB.getParent() &&

           "Basic block is in a different function");

  }

  /// Set the insertion point to before MI.

  /// \pre MI must be in getMF().

  void setInstr(MachineInstr &MI) {

    assert(MI.getParent() && "Instruction is not part of a basic block");

    setMBB(*MI.getParent());

    State.II = MI.getIterator();

    setPCSections(MI.getPCSections());

  }

  /// @}

  /// Set the insertion point to before MI, and set the debug loc to MI's loc.

  /// \pre MI must be in getMF().

  void setInstrAndDebugLoc(MachineInstr &MI) {

    setInstr(MI);

    setDebugLoc(MI.getDebugLoc());

  }

  void setChangeObserver(GISelChangeObserver &Observer) {

    State.Observer = &Observer;

  }

  void stopObservingChanges() { State.Observer = nullptr; }

  /// @}

  /// Set the debug location to \p DL for all the next build instructions.

  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }

  /// Get the current instruction's debug location.

  const DebugLoc &getDebugLoc() { return State.DL; }

  /// Set the PC sections metadata to \p MD for all the next build instructions.

  void setPCSections(MDNode *MD) { State.PCSections = MD; }

  /// Get the current instruction's PC sections metadata.

  MDNode *getPCSections() { return State.PCSections; }

  /// Build and insert <empty> = \p Opcode <empty>.

  /// The insertion point is the one set by the last call of either

  /// setBasicBlock or setMI.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildInstr(unsigned Opcode) {

    return insertInstr(buildInstrNoInsert(Opcode));

  }

  /// Build but don't insert <empty> = \p Opcode <empty>.

  ///

  /// \pre setMF, setBasicBlock or setMI  must have been called.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);

  /// Insert an existing instruction at the insertion point.

  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);

  /// Build and insert a DBG_VALUE instruction expressing the fact that the

  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).

  MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,

                                          const MDNode *Expr);

  /// Build and insert a DBG_VALUE instruction expressing the fact that the

  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p

  /// Expr).

  MachineInstrBuilder buildIndirectDbgValue(Register Reg,

                                            const MDNode *Variable,

                                            const MDNode *Expr);

  /// Build and insert a DBG_VALUE instruction expressing the fact that the

  /// associated \p Variable lives in the stack slot specified by \p FI

  /// (suitably modified by \p Expr).

  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,

                                      const MDNode *Expr);

  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is

  /// given by \p C (suitably modified by \p Expr).

  MachineInstrBuilder buildConstDbgValue(const Constant &C,

                                         const MDNode *Variable,

                                         const MDNode *Expr);

  /// Build and insert a DBG_LABEL instructions specifying that \p Label is

  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".

  MachineInstrBuilder buildDbgLabel(const MDNode *Label);

  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align

  ///

  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of

  /// the allocated memory into \p Res.

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with pointer type.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,

                                         Align Alignment);

  /// Build and insert \p Res = G_FRAME_INDEX \p Idx

  ///

  /// G_FRAME_INDEX materializes the address of an alloca value or other

  /// stack-based object.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with pointer type.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);

  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV

  ///

  /// G_GLOBAL_VALUE materializes the address of the specified global

  /// into \p Res.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with pointer type

  ///      in the same address space as \p GV.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);

  /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1

  ///

  /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,

  /// storing the resulting pointer in \p Res. Addressible units are typically

  /// bytes but this can vary between targets.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer

  ///      type.

  /// \pre \p Op1 must be a generic virtual register with scalar type.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,

                                  const SrcOp &Op1);

  /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)

  ///

  /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,

  /// storing the resulting pointer in \p Res. If \p Value is zero then no

  /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to

  /// \p Res.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Op0 must be a generic virtual register with pointer type.

  /// \pre \p ValueTy must be a scalar type.

  /// \pre \p Res must be 0. This is to detect confusion between

  ///      materializePtrAdd() and buildPtrAdd().

  /// \post \p Res will either be a new generic virtual register of the same

  ///       type as \p Op0 or \p Op0 itself.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,

                                                       Register Op0,

                                                       const LLT ValueTy,

                                                       uint64_t Value);

  /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1

  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,

                                   const SrcOp &Op1) {

    return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});

  }

  /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1

  ///

  /// This clears the low bits of a pointer operand without destroying its

  /// pointer properties. This has the effect of rounding the address *down* to

  /// a specified alignment in bits.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer

  ///      type.

  /// \pre \p NumBits must be an integer representing the number of low bits to

  ///      be cleared in \p Op0.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,

                                          uint32_t NumBits);

  /// Build and insert

  /// a, b, ..., x = G_UNMERGE_VALUES \p Op0

  /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef

  ///

  /// Pad \p Op0 with undef elements to match number of elements in \p Res.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,

  ///      same vector element type and Op0 must have fewer elements then Res.

  ///

  /// \return a MachineInstrBuilder for the newly created build vector instr.

  MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res,

                                                      const SrcOp &Op0);

  /// Build and insert

  /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0

  /// \p Res = G_BUILD_VECTOR a, b, ..., x

  ///

  /// Delete trailing elements in \p Op0 to match number of elements in \p Res.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,

  ///      same vector element type and Op0 must have more elements then Res.

  ///

  /// \return a MachineInstrBuilder for the newly created build vector instr.

  MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res,

                                                        const SrcOp &Op0);

  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1

  ///

  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and

  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the

  /// same scalar type.

  ////\pre \p CarryOut must be generic virtual register with scalar type

  ///(typically s1)

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1) {

    return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});

  }

  /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1

  MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1) {

    return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});

  }

  /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1

  MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1) {

    return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});

  }

  /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1

  MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1) {

    return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});

  }

  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,

  /// \p Op1, \p CarryIn

  ///

  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit

  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned

  /// arithmetic.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers

  ///      with the same scalar type.

  /// \pre \p CarryOut and \p CarryIn must be generic virtual

  ///      registers with the same scalar type (typically s1)

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1,

                                 const SrcOp &CarryIn) {

    return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},

                                             {Op0, Op1, CarryIn});

  }

  /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp

  MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1,

                                 const SrcOp &CarryIn) {

    return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},

                                             {Op0, Op1, CarryIn});

  }

  /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp

  MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1,

                                 const SrcOp &CarryIn) {

    return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},

                                             {Op0, Op1, CarryIn});

  }

  /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp

  MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,

                                 const SrcOp &Op0, const SrcOp &Op1,

                                 const SrcOp &CarryIn) {

    return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},

                                             {Op0, Op1, CarryIn});

  }

  /// Build and insert \p Res = G_ANYEXT \p Op0

  ///

  /// G_ANYEXT produces a register of the specified width, with bits 0 to

  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified

  /// (i.e. this is neither zero nor sign-extension). For a vector register,

  /// each element is extended individually.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be smaller than \p Res

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);

  /// Build and insert \p Res = G_SEXT \p Op

  ///

  /// G_SEXT produces a register of the specified width, with bits 0 to

  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the

  /// high bit of \p Op (i.e. 2s-complement sign extended).

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be smaller than \p Res

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);

  /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp

  MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {

    return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});

  }

  /// Build and insert \p Res = G_FPEXT \p Op

  MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op,

                                 std::optional<unsigned> Flags = std::nullopt) {

    return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);

  }

  /// Build and insert a G_PTRTOINT instruction.

  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {

    return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});

  }

  /// Build and insert a G_INTTOPTR instruction.

  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {

    return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});

  }

  /// Build and insert \p Dst = G_BITCAST \p Src

  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {

    return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});

  }

    /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src

  MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {

    return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});

  }

  /// \return The opcode of the extension the target wants to use for boolean

  /// values.

  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;

  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res

  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.

  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,

                                   bool IsFP);

  // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,

  // or COPY depending on how the target wants to extend boolean values, using

  // the original register size.

  MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,

                                        bool IsVector,

                                        bool IsFP);

  /// Build and insert \p Res = G_ZEXT \p Op

  ///

  /// G_ZEXT produces a register of the specified width, with bits 0 to

  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector

  /// register, each element is extended individually.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be smaller than \p Res

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);

  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or

  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.

  ///  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);

  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or

  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.

  ///  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);

  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or

  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.

  ///  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);

  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p

  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and

  /// \p Op.

  ///  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or vector type.

  /// \pre \p Op must be a generic virtual register with scalar or vector type.

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,

                                      const SrcOp &Op);

  /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)

  /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is

  /// emulated using G_AND.

  MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,

                                     int64_t ImmOp);

  /// Build and insert an appropriate cast between two registers of equal size.

  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);

  /// Build and insert G_BR \p Dest

  ///

  /// G_BR is an unconditional branch to \p Dest.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);

  /// Build and insert G_BRCOND \p Tst, \p Dest

  ///

  /// G_BRCOND is a conditional branch to \p Dest.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Tst must be a generic virtual register with scalar

  ///      type. At the beginning of legalization, this will be a single

  ///      bit (s1). Targets with interesting flags registers may change

  ///      this. For a wider type, whether the branch is taken must only

  ///      depend on bit 0 (for now).

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest);

  /// Build and insert G_BRINDIRECT \p Tgt

  ///

  /// G_BRINDIRECT is an indirect branch to \p Tgt.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Tgt must be a generic virtual register with pointer type.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildBrIndirect(Register Tgt);

  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg

  ///

  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,

  /// jump table index \p JTI and index \p IndexReg

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p TablePtr must be a generic virtual register with pointer type.

  /// \pre \p JTI must be be a jump table index.

  /// \pre \p IndexReg must be a generic virtual register with pointer type.

  ///

  /// \return a MachineInstrBuilder for the newly created instruction.

  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,

                                Register IndexReg);

  /// Build and insert \p Res = G_CONSTANT \p Val

  ///

  /// G_CONSTANT is an integer constant with the specified size and value. \p

  /// Val will be extended or truncated to the size of \p Reg.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar or pointer

  ///      type.

  ///

  /// \return The newly created instruction.

  virtual MachineInstrBuilder buildConstant(const DstOp &Res,

                                            const ConstantInt &Val);

  /// Build and insert \p Res = G_CONSTANT \p Val

  ///

  /// G_CONSTANT is an integer constant with the specified size and value.

  ///

  /// \pre setBasicBlock or setMI must have been called.

  /// \pre \p Res must be a generic virtual register with scalar type.

  ///

  /// \return The newly created instruction.

  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);

  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);

  /// Build and insert \p Res = G_FCONSTANT \p Val