Subversion Repositories QNX 8.QNX8 LLVM/Clang compiler suite

//===- TargetTransformInfo.h ------------------------------------*- C++ -*-===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

/// \file

/// This pass exposes codegen information to IR-level passes. Every

/// transformation that uses codegen information is broken into three parts:

/// 1. The IR-level analysis pass.

/// 2. The IR-level transformation interface which provides the needed

///    information.

/// 3. Codegen-level implementation which uses target-specific hooks.

///

/// This file defines #2, which is the interface that IR-level transformations

/// use for querying the codegen.

///

//===----------------------------------------------------------------------===//

#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H

#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H

#include "llvm/ADT/SmallBitVector.h"

#include "llvm/IR/FMF.h"

#include "llvm/IR/InstrTypes.h"

#include "llvm/IR/PassManager.h"

#include "llvm/Pass.h"

#include "llvm/Support/AtomicOrdering.h"

#include "llvm/Support/BranchProbability.h"

#include "llvm/Support/InstructionCost.h"

#include <functional>

#include <optional>

#include <utility>

namespace llvm {

namespace Intrinsic {

typedef unsigned ID;

}

class AssumptionCache;

class BlockFrequencyInfo;

class DominatorTree;

class BranchInst;

class CallBase;

class Function;

class GlobalValue;

class InstCombiner;

class OptimizationRemarkEmitter;

class InterleavedAccessInfo;

class IntrinsicInst;

class LoadInst;

class Loop;

class LoopInfo;

class LoopVectorizationLegality;

class ProfileSummaryInfo;

class RecurrenceDescriptor;

class SCEV;

class ScalarEvolution;

class StoreInst;

class SwitchInst;

class TargetLibraryInfo;

class Type;

class User;

class Value;

class VPIntrinsic;

struct KnownBits;

/// Information about a load/store intrinsic defined by the target.

struct MemIntrinsicInfo {

  /// This is the pointer that the intrinsic is loading from or storing to.

  /// If this is non-null, then analysis/optimization passes can assume that

  /// this intrinsic is functionally equivalent to a load/store from this

  /// pointer.

  Value *PtrVal = nullptr;

  // Ordering for atomic operations.

  AtomicOrdering Ordering = AtomicOrdering::NotAtomic;

  // Same Id is set by the target for corresponding load/store intrinsics.

  unsigned short MatchingId = 0;

  bool ReadMem = false;

  bool WriteMem = false;

  bool IsVolatile = false;

  bool isUnordered() const {

    return (Ordering == AtomicOrdering::NotAtomic ||

            Ordering == AtomicOrdering::Unordered) &&

           !IsVolatile;

  }

};

/// Attributes of a target dependent hardware loop.

struct HardwareLoopInfo {

  HardwareLoopInfo() = delete;

  HardwareLoopInfo(Loop *L) : L(L) {}

  Loop *L = nullptr;

  BasicBlock *ExitBlock = nullptr;

  BranchInst *ExitBranch = nullptr;

  const SCEV *ExitCount = nullptr;

  IntegerType *CountType = nullptr;

  Value *LoopDecrement = nullptr; // Decrement the loop counter by this

                                  // value in every iteration.

  bool IsNestingLegal = false;    // Can a hardware loop be a parent to

                                  // another hardware loop?

  bool CounterInReg = false;      // Should loop counter be updated in

                                  // the loop via a phi?

  bool PerformEntryTest = false;  // Generate the intrinsic which also performs

                                  // icmp ne zero on the loop counter value and

                                  // produces an i1 to guard the loop entry.

  bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI,

                               DominatorTree &DT, bool ForceNestedLoop = false,

                               bool ForceHardwareLoopPHI = false);

  bool canAnalyze(LoopInfo &LI);

};

class IntrinsicCostAttributes {

  const IntrinsicInst *II = nullptr;

  Type *RetTy = nullptr;

  Intrinsic::ID IID;

  SmallVector<Type *, 4> ParamTys;

  SmallVector<const Value *, 4> Arguments;

  FastMathFlags FMF;

  // If ScalarizationCost is UINT_MAX, the cost of scalarizing the

  // arguments and the return value will be computed based on types.

  InstructionCost ScalarizationCost = InstructionCost::getInvalid();

public:

  IntrinsicCostAttributes(

      Intrinsic::ID Id, const CallBase &CI,

      InstructionCost ScalarCost = InstructionCost::getInvalid(),

      bool TypeBasedOnly = false);

  IntrinsicCostAttributes(

      Intrinsic::ID Id, Type *RTy, ArrayRef<Type *> Tys,

      FastMathFlags Flags = FastMathFlags(), const IntrinsicInst *I = nullptr,

      InstructionCost ScalarCost = InstructionCost::getInvalid());

  IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy,

                          ArrayRef<const Value *> Args);

  IntrinsicCostAttributes(

      Intrinsic::ID Id, Type *RTy, ArrayRef<const Value *> Args,

      ArrayRef<Type *> Tys, FastMathFlags Flags = FastMathFlags(),

      const IntrinsicInst *I = nullptr,

      InstructionCost ScalarCost = InstructionCost::getInvalid());

  Intrinsic::ID getID() const { return IID; }

  const IntrinsicInst *getInst() const { return II; }

  Type *getReturnType() const { return RetTy; }

  FastMathFlags getFlags() const { return FMF; }

  InstructionCost getScalarizationCost() const { return ScalarizationCost; }

  const SmallVectorImpl<const Value *> &getArgs() const { return Arguments; }

  const SmallVectorImpl<Type *> &getArgTypes() const { return ParamTys; }

  bool isTypeBasedOnly() const {

    return Arguments.empty();

  }

  bool skipScalarizationCost() const { return ScalarizationCost.isValid(); }

};

enum class PredicationStyle { None, Data, DataAndControlFlow };

class TargetTransformInfo;

typedef TargetTransformInfo TTI;

/// This pass provides access to the codegen interfaces that are needed

/// for IR-level transformations.

class TargetTransformInfo {

public:

  /// Construct a TTI object using a type implementing the \c Concept

  /// API below.

  ///

  /// This is used by targets to construct a TTI wrapping their target-specific

  /// implementation that encodes appropriate costs for their target.

  template <typename T> TargetTransformInfo(T Impl);

  /// Construct a baseline TTI object using a minimal implementation of

  /// the \c Concept API below.

  ///

  /// The TTI implementation will reflect the information in the DataLayout

  /// provided if non-null.

  explicit TargetTransformInfo(const DataLayout &DL);

  // Provide move semantics.

  TargetTransformInfo(TargetTransformInfo &&Arg);

  TargetTransformInfo &operator=(TargetTransformInfo &&RHS);

  // We need to define the destructor out-of-line to define our sub-classes

  // out-of-line.

  ~TargetTransformInfo();

  /// Handle the invalidation of this information.

  ///

  /// When used as a result of \c TargetIRAnalysis this method will be called

  /// when the function this was computed for changes. When it returns false,

  /// the information is preserved across those changes.

  bool invalidate(Function &, const PreservedAnalyses &,

                  FunctionAnalysisManager::Invalidator &) {

    // FIXME: We should probably in some way ensure that the subtarget

    // information for a function hasn't changed.

    return false;

  }

  /// \name Generic Target Information

  /// @{

  /// The kind of cost model.

  ///

  /// There are several different cost models that can be customized by the

  /// target. The normalization of each cost model may be target specific.

  /// e.g. TCK_SizeAndLatency should be comparable to target thresholds such as

  /// those derived from MCSchedModel::LoopMicroOpBufferSize etc.

  enum TargetCostKind {

    TCK_RecipThroughput, ///< Reciprocal throughput.

    TCK_Latency,         ///< The latency of instruction.

    TCK_CodeSize,        ///< Instruction code size.

    TCK_SizeAndLatency   ///< The weighted sum of size and latency.

  };

  /// Underlying constants for 'cost' values in this interface.

  ///

  /// Many APIs in this interface return a cost. This enum defines the

  /// fundamental values that should be used to interpret (and produce) those

  /// costs. The costs are returned as an int rather than a member of this

  /// enumeration because it is expected that the cost of one IR instruction

  /// may have a multiplicative factor to it or otherwise won't fit directly

  /// into the enum. Moreover, it is common to sum or average costs which works

  /// better as simple integral values. Thus this enum only provides constants.

  /// Also note that the returned costs are signed integers to make it natural

  /// to add, subtract, and test with zero (a common boundary condition). It is

  /// not expected that 2^32 is a realistic cost to be modeling at any point.

  ///

  /// Note that these costs should usually reflect the intersection of code-size

  /// cost and execution cost. A free instruction is typically one that folds

  /// into another instruction. For example, reg-to-reg moves can often be

  /// skipped by renaming the registers in the CPU, but they still are encoded

  /// and thus wouldn't be considered 'free' here.

  enum TargetCostConstants {

    TCC_Free = 0,     ///< Expected to fold away in lowering.

    TCC_Basic = 1,    ///< The cost of a typical 'add' instruction.

    TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.

  };

  /// Estimate the cost of a GEP operation when lowered.

  InstructionCost

  getGEPCost(Type *PointeeType, const Value *Ptr,

             ArrayRef<const Value *> Operands,

             TargetCostKind CostKind = TCK_SizeAndLatency) const;

  /// \returns A value by which our inlining threshold should be multiplied.

  /// This is primarily used to bump up the inlining threshold wholesale on

  /// targets where calls are unusually expensive.

  ///

  /// TODO: This is a rather blunt instrument.  Perhaps altering the costs of

  /// individual classes of instructions would be better.

  unsigned getInliningThresholdMultiplier() const;

  /// \returns A value to be added to the inlining threshold.

  unsigned adjustInliningThreshold(const CallBase *CB) const;

  /// \returns Vector bonus in percent.

  ///

  /// Vector bonuses: We want to more aggressively inline vector-dense kernels

  /// and apply this bonus based on the percentage of vector instructions. A

  /// bonus is applied if the vector instructions exceed 50% and half that

  /// amount is applied if it exceeds 10%. Note that these bonuses are some what

  /// arbitrary and evolved over time by accident as much as because they are

  /// principled bonuses.

  /// FIXME: It would be nice to base the bonus values on something more

  /// scientific. A target may has no bonus on vector instructions.

  int getInlinerVectorBonusPercent() const;

  /// \return the expected cost of a memcpy, which could e.g. depend on the

  /// source/destination type and alignment and the number of bytes copied.

  InstructionCost getMemcpyCost(const Instruction *I) const;

  /// \return The estimated number of case clusters when lowering \p 'SI'.

  /// \p JTSize Set a jump table size only when \p SI is suitable for a jump

  /// table.

  unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,

                                            unsigned &JTSize,

                                            ProfileSummaryInfo *PSI,

                                            BlockFrequencyInfo *BFI) const;

  /// Estimate the cost of a given IR user when lowered.

  ///

  /// This can estimate the cost of either a ConstantExpr or Instruction when

  /// lowered.

  ///

  /// \p Operands is a list of operands which can be a result of transformations

  /// of the current operands. The number of the operands on the list must equal

  /// to the number of the current operands the IR user has. Their order on the

  /// list must be the same as the order of the current operands the IR user

  /// has.

  ///

  /// The returned cost is defined in terms of \c TargetCostConstants, see its

  /// comments for a detailed explanation of the cost values.

  InstructionCost getInstructionCost(const User *U,

                                     ArrayRef<const Value *> Operands,

                                     TargetCostKind CostKind) const;

  /// This is a helper function which calls the three-argument

  /// getInstructionCost with \p Operands which are the current operands U has.

  InstructionCost getInstructionCost(const User *U,

                                     TargetCostKind CostKind) const {

    SmallVector<const Value *, 4> Operands(U->operand_values());

    return getInstructionCost(U, Operands, CostKind);

  }

  /// If a branch or a select condition is skewed in one direction by more than

  /// this factor, it is very likely to be predicted correctly.

  BranchProbability getPredictableBranchThreshold() const;

  /// Return true if branch divergence exists.

  ///

  /// Branch divergence has a significantly negative impact on GPU performance

  /// when threads in the same wavefront take different paths due to conditional

  /// branches.

  bool hasBranchDivergence() const;

  /// Return true if the target prefers to use GPU divergence analysis to

  /// replace the legacy version.

  bool useGPUDivergenceAnalysis() const;

  /// Returns whether V is a source of divergence.

  ///

  /// This function provides the target-dependent information for

  /// the target-independent LegacyDivergenceAnalysis. LegacyDivergenceAnalysis

  /// first builds the dependency graph, and then runs the reachability

  /// algorithm starting with the sources of divergence.

  bool isSourceOfDivergence(const Value *V) const;

  // Returns true for the target specific

  // set of operations which produce uniform result

  // even taking non-uniform arguments

  bool isAlwaysUniform(const Value *V) const;

  /// Returns the address space ID for a target's 'flat' address space. Note

  /// this is not necessarily the same as addrspace(0), which LLVM sometimes

  /// refers to as the generic address space. The flat address space is a

  /// generic address space that can be used access multiple segments of memory

  /// with different address spaces. Access of a memory location through a

  /// pointer with this address space is expected to be legal but slower

  /// compared to the same memory location accessed through a pointer with a

  /// different address space.

  //

  /// This is for targets with different pointer representations which can

  /// be converted with the addrspacecast instruction. If a pointer is converted

  /// to this address space, optimizations should attempt to replace the access

  /// with the source address space.

  ///

  /// \returns ~0u if the target does not have such a flat address space to

  /// optimize away.

  unsigned getFlatAddressSpace() const;

  /// Return any intrinsic address operand indexes which may be rewritten if

  /// they use a flat address space pointer.

  ///

  /// \returns true if the intrinsic was handled.

  bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,

                                  Intrinsic::ID IID) const;

  bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;

  /// Return true if globals in this address space can have initializers other

  /// than `undef`.

  bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const;

  unsigned getAssumedAddrSpace(const Value *V) const;

  bool isSingleThreaded() const;

  std::pair<const Value *, unsigned>

  getPredicatedAddrSpace(const Value *V) const;

  /// Rewrite intrinsic call \p II such that \p OldV will be replaced with \p

  /// NewV, which has a different address space. This should happen for every

  /// operand index that collectFlatAddressOperands returned for the intrinsic.

  /// \returns nullptr if the intrinsic was not handled. Otherwise, returns the

  /// new value (which may be the original \p II with modified operands).

  Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,

                                          Value *NewV) const;

  /// Test whether calls to a function lower to actual program function

  /// calls.

  ///

  /// The idea is to test whether the program is likely to require a 'call'

  /// instruction or equivalent in order to call the given function.

  ///

  /// FIXME: It's not clear that this is a good or useful query API. Client's

  /// should probably move to simpler cost metrics using the above.

  /// Alternatively, we could split the cost interface into distinct code-size

  /// and execution-speed costs. This would allow modelling the core of this

  /// query more accurately as a call is a single small instruction, but

  /// incurs significant execution cost.

  bool isLoweredToCall(const Function *F) const;

  struct LSRCost {

    /// TODO: Some of these could be merged. Also, a lexical ordering

    /// isn't always optimal.

    unsigned Insns;

    unsigned NumRegs;

    unsigned AddRecCost;

    unsigned NumIVMuls;

    unsigned NumBaseAdds;

    unsigned ImmCost;

    unsigned SetupCost;

    unsigned ScaleCost;

  };

  /// Parameters that control the generic loop unrolling transformation.

  struct UnrollingPreferences {

    /// The cost threshold for the unrolled loop. Should be relative to the

    /// getInstructionCost values returned by this API, and the expectation is

    /// that the unrolled loop's instructions when run through that interface

    /// should not exceed this cost. However, this is only an estimate. Also,

    /// specific loops may be unrolled even with a cost above this threshold if

    /// deemed profitable. Set this to UINT_MAX to disable the loop body cost

    /// restriction.

    unsigned Threshold;

    /// If complete unrolling will reduce the cost of the loop, we will boost

    /// the Threshold by a certain percent to allow more aggressive complete

    /// unrolling. This value provides the maximum boost percentage that we

    /// can apply to Threshold (The value should be no less than 100).

    /// BoostedThreshold = Threshold * min(RolledCost / UnrolledCost,

    ///                                    MaxPercentThresholdBoost / 100)

    /// E.g. if complete unrolling reduces the loop execution time by 50%

    /// then we boost the threshold by the factor of 2x. If unrolling is not

    /// expected to reduce the running time, then we do not increase the

    /// threshold.

    unsigned MaxPercentThresholdBoost;

    /// The cost threshold for the unrolled loop when optimizing for size (set

    /// to UINT_MAX to disable).

    unsigned OptSizeThreshold;

    /// The cost threshold for the unrolled loop, like Threshold, but used

    /// for partial/runtime unrolling (set to UINT_MAX to disable).

    unsigned PartialThreshold;

    /// The cost threshold for the unrolled loop when optimizing for size, like

    /// OptSizeThreshold, but used for partial/runtime unrolling (set to

    /// UINT_MAX to disable).

    unsigned PartialOptSizeThreshold;

    /// A forced unrolling factor (the number of concatenated bodies of the

    /// original loop in the unrolled loop body). When set to 0, the unrolling

    /// transformation will select an unrolling factor based on the current cost

    /// threshold and other factors.

    unsigned Count;

    /// Default unroll count for loops with run-time trip count.

    unsigned DefaultUnrollRuntimeCount;

    // Set the maximum unrolling factor. The unrolling factor may be selected

    // using the appropriate cost threshold, but may not exceed this number

    // (set to UINT_MAX to disable). This does not apply in cases where the

    // loop is being fully unrolled.

    unsigned MaxCount;

    /// Set the maximum unrolling factor for full unrolling. Like MaxCount, but

    /// applies even if full unrolling is selected. This allows a target to fall

    /// back to Partial unrolling if full unrolling is above FullUnrollMaxCount.

    unsigned FullUnrollMaxCount;

    // Represents number of instructions optimized when "back edge"

    // becomes "fall through" in unrolled loop.

    // For now we count a conditional branch on a backedge and a comparison

    // feeding it.

    unsigned BEInsns;

    /// Allow partial unrolling (unrolling of loops to expand the size of the

    /// loop body, not only to eliminate small constant-trip-count loops).

    bool Partial;

    /// Allow runtime unrolling (unrolling of loops to expand the size of the

    /// loop body even when the number of loop iterations is not known at

    /// compile time).

    bool Runtime;

    /// Allow generation of a loop remainder (extra iterations after unroll).

    bool AllowRemainder;

    /// Allow emitting expensive instructions (such as divisions) when computing

    /// the trip count of a loop for runtime unrolling.

    bool AllowExpensiveTripCount;

    /// Apply loop unroll on any kind of loop

    /// (mainly to loops that fail runtime unrolling).

    bool Force;

    /// Allow using trip count upper bound to unroll loops.

    bool UpperBound;

    /// Allow unrolling of all the iterations of the runtime loop remainder.

    bool UnrollRemainder;

    /// Allow unroll and jam. Used to enable unroll and jam for the target.

    bool UnrollAndJam;

    /// Threshold for unroll and jam, for inner loop size. The 'Threshold'

    /// value above is used during unroll and jam for the outer loop size.

    /// This value is used in the same manner to limit the size of the inner

    /// loop.

    unsigned UnrollAndJamInnerLoopThreshold;

    /// Don't allow loop unrolling to simulate more than this number of

    /// iterations when checking full unroll profitability

    unsigned MaxIterationsCountToAnalyze;

  };

  /// Get target-customized preferences for the generic loop unrolling

  /// transformation. The caller will initialize UP with the current

  /// target-independent defaults.

  void getUnrollingPreferences(Loop *L, ScalarEvolution &,

                               UnrollingPreferences &UP,

                               OptimizationRemarkEmitter *ORE) const;

  /// Query the target whether it would be profitable to convert the given loop

  /// into a hardware loop.

  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,

                                AssumptionCache &AC, TargetLibraryInfo *LibInfo,

                                HardwareLoopInfo &HWLoopInfo) const;

  /// Query the target whether it would be prefered to create a predicated

  /// vector loop, which can avoid the need to emit a scalar epilogue loop.

  bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,

                                   AssumptionCache &AC, TargetLibraryInfo *TLI,

                                   DominatorTree *DT,

                                   LoopVectorizationLegality *LVL,

                                   InterleavedAccessInfo *IAI) const;

  /// Query the target whether lowering of the llvm.get.active.lane.mask

  /// intrinsic is supported and how the mask should be used. A return value

  /// of PredicationStyle::Data indicates the mask is used as data only,

  /// whereas PredicationStyle::DataAndControlFlow indicates we should also use

  /// the mask for control flow in the loop. If unsupported the return value is

  /// PredicationStyle::None.

  PredicationStyle emitGetActiveLaneMask() const;

  // Parameters that control the loop peeling transformation

  struct PeelingPreferences {

    /// A forced peeling factor (the number of bodied of the original loop

    /// that should be peeled off before the loop body). When set to 0, the

    /// a peeling factor based on profile information and other factors.

    unsigned PeelCount;

    /// Allow peeling off loop iterations.

    bool AllowPeeling;

    /// Allow peeling off loop iterations for loop nests.

    bool AllowLoopNestsPeeling;

    /// Allow peeling basing on profile. Uses to enable peeling off all

    /// iterations basing on provided profile.

    /// If the value is true the peeling cost model can decide to peel only

    /// some iterations and in this case it will set this to false.

    bool PeelProfiledIterations;

  };

  /// Get target-customized preferences for the generic loop peeling

  /// transformation. The caller will initialize \p PP with the current

  /// target-independent defaults with information from \p L and \p SE.

  void getPeelingPreferences(Loop *L, ScalarEvolution &SE,

                             PeelingPreferences &PP) const;

  /// Targets can implement their own combinations for target-specific

  /// intrinsics. This function will be called from the InstCombine pass every

  /// time a target-specific intrinsic is encountered.

  ///

  /// \returns std::nullopt to not do anything target specific or a value that

  /// will be returned from the InstCombiner. It is possible to return null and

  /// stop further processing of the intrinsic by returning nullptr.

  std::optional<Instruction *> instCombineIntrinsic(InstCombiner & IC,

                                                    IntrinsicInst & II) const;

  /// Can be used to implement target-specific instruction combining.

  /// \see instCombineIntrinsic

  std::optional<Value *> simplifyDemandedUseBitsIntrinsic(

      InstCombiner & IC, IntrinsicInst & II, APInt DemandedMask,

      KnownBits & Known, bool &KnownBitsComputed) const;

  /// Can be used to implement target-specific instruction combining.

  /// \see instCombineIntrinsic

  std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(

      InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts,

      APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3,

      std::function<void(Instruction *, unsigned, APInt, APInt &)>

          SimplifyAndSetOp) const;

  /// @}

  /// \name Scalar Target Information

  /// @{

  /// Flags indicating the kind of support for population count.

  ///

  /// Compared to the SW implementation, HW support is supposed to

  /// significantly boost the performance when the population is dense, and it

  /// may or may not degrade performance if the population is sparse. A HW

  /// support is considered as "Fast" if it can outperform, or is on a par

  /// with, SW implementation when the population is sparse; otherwise, it is

  /// considered as "Slow".

  enum PopcntSupportKind { PSK_Software, PSK_SlowHardware, PSK_FastHardware };

  /// Return true if the specified immediate is legal add immediate, that

  /// is the target has add instructions which can add a register with the

  /// immediate without having to materialize the immediate into a register.

  bool isLegalAddImmediate(int64_t Imm) const;

  /// Return true if the specified immediate is legal icmp immediate,

  /// that is the target has icmp instructions which can compare a register

  /// against the immediate without having to materialize the immediate into a

  /// register.

  bool isLegalICmpImmediate(int64_t Imm) const;

  /// Return true if the addressing mode represented by AM is legal for

  /// this target, for a load/store of the specified type.

  /// The type may be VoidTy, in which case only return true if the addressing

  /// mode is legal for a load/store of any legal type.

  /// If target returns true in LSRWithInstrQueries(), I may be valid.

  /// TODO: Handle pre/postinc as well.

  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,

                             bool HasBaseReg, int64_t Scale,

                             unsigned AddrSpace = 0,

                             Instruction *I = nullptr) const;

  /// Return true if LSR cost of C1 is lower than C2.

  bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,

                     const TargetTransformInfo::LSRCost &C2) const;

  /// Return true if LSR major cost is number of registers. Targets which

  /// implement their own isLSRCostLess and unset number of registers as major

  /// cost should return false, otherwise return true.

  bool isNumRegsMajorCostOfLSR() const;

  /// \returns true if LSR should not optimize a chain that includes \p I.

  bool isProfitableLSRChainElement(Instruction *I) const;

  /// Return true if the target can fuse a compare and branch.

  /// Loop-strength-reduction (LSR) uses that knowledge to adjust its cost

  /// calculation for the instructions in a loop.

  bool canMacroFuseCmp() const;

  /// Return true if the target can save a compare for loop count, for example

  /// hardware loop saves a compare.

  bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,

                  DominatorTree *DT, AssumptionCache *AC,

                  TargetLibraryInfo *LibInfo) const;

  enum AddressingModeKind {

    AMK_PreIndexed,

    AMK_PostIndexed,

    AMK_None

  };

  /// Return the preferred addressing mode LSR should make efforts to generate.

  AddressingModeKind getPreferredAddressingMode(const Loop *L,

                                                ScalarEvolution *SE) const;

  /// Return true if the target supports masked store.

  bool isLegalMaskedStore(Type *DataType, Align Alignment) const;

  /// Return true if the target supports masked load.

  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const;

  /// Return true if the target supports nontemporal store.

  bool isLegalNTStore(Type *DataType, Align Alignment) const;

  /// Return true if the target supports nontemporal load.

  bool isLegalNTLoad(Type *DataType, Align Alignment) const;

  /// \Returns true if the target supports broadcasting a load to a vector of

  /// type <NumElements x ElementTy>.

  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;

  /// Return true if the target supports masked scatter.

  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const;

  /// Return true if the target supports masked gather.

  bool isLegalMaskedGather(Type *DataType, Align Alignment) const;

  /// Return true if the target forces scalarizing of llvm.masked.gather

  /// intrinsics.

  bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const;

  /// Return true if the target forces scalarizing of llvm.masked.scatter

  /// intrinsics.

  bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const;

  /// Return true if the target supports masked compress store.

  bool isLegalMaskedCompressStore(Type *DataType) const;

  /// Return true if the target supports masked expand load.

  bool isLegalMaskedExpandLoad(Type *DataType) const;

  /// Return true if this is an alternating opcode pattern that can be lowered

  /// to a single instruction on the target. In X86 this is for the addsub

  /// instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR.

  /// This function expectes two opcodes: \p Opcode1 and \p Opcode2 being

  /// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`

  /// when \p Opcode0 is selected and `1` when Opcode1 is selected.

  /// \p VecTy is the vector type of the instruction to be generated.

  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,

                       const SmallBitVector &OpcodeMask) const;

  /// Return true if we should be enabling ordered reductions for the target.

  bool enableOrderedReductions() const;

  /// Return true if the target has a unified operation to calculate division

  /// and remainder. If so, the additional implicit multiplication and

  /// subtraction required to calculate a remainder from division are free. This

  /// can enable more aggressive transformations for division and remainder than

  /// would typically be allowed using throughput or size cost models.

  bool hasDivRemOp(Type *DataType, bool IsSigned) const;

  /// Return true if the given instruction (assumed to be a memory access

  /// instruction) has a volatile variant. If that's the case then we can avoid

  /// addrspacecast to generic AS for volatile loads/stores. Default

  /// implementation returns false, which prevents address space inference for

  /// volatile loads/stores.

  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;

  /// Return true if target doesn't mind addresses in vectors.

  bool prefersVectorizedAddressing() const;

  /// Return the cost of the scaling factor used in the addressing

  /// mode represented by AM for this target, for a load/store

  /// of the specified type.

  /// If the AM is supported, the return value must be >= 0.

  /// If the AM is not supported, it returns a negative value.

  /// TODO: Handle pre/postinc as well.

  InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,

                                       int64_t BaseOffset, bool HasBaseReg,

                                       int64_t Scale,

                                       unsigned AddrSpace = 0) const;

  /// Return true if the loop strength reduce pass should make

  /// Instruction* based TTI queries to isLegalAddressingMode(). This is

  /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned

  /// immediate offset and no index register.

  bool LSRWithInstrQueries() const;

  /// Return true if it's free to truncate a value of type Ty1 to type

  /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16

  /// by referencing its sub-register AX.

  bool isTruncateFree(Type *Ty1, Type *Ty2) const;

  /// Return true if it is profitable to hoist instruction in the

  /// then/else to before if.

  bool isProfitableToHoist(Instruction *I) const;

  bool useAA() const;

  /// Return true if this type is legal.

  bool isTypeLegal(Type *Ty) const;

  /// Returns the estimated number of registers required to represent \p Ty.

  unsigned getRegUsageForType(Type *Ty) const;

  /// Return true if switches should be turned into lookup tables for the

  /// target.

  bool shouldBuildLookupTables() const;

  /// Return true if switches should be turned into lookup tables

  /// containing this constant value for the target.

  bool shouldBuildLookupTablesForConstant(Constant *C) const;

  /// Return true if lookup tables should be turned into relative lookup tables.

  bool shouldBuildRelLookupTables() const;

  /// Return true if the input function which is cold at all call sites,

  ///  should use coldcc calling convention.

  bool useColdCCForColdCall(Function &F) const;

  /// Estimate the overhead of scalarizing an instruction. Insert and Extract

  /// are set if the demanded result elements need to be inserted and/or

  /// extracted from vectors.

  InstructionCost getScalarizationOverhead(VectorType *Ty,

                                           const APInt &DemandedElts,

                                           bool Insert, bool Extract,

                                           TTI::TargetCostKind CostKind) const;

  /// Estimate the overhead of scalarizing an instructions unique

  /// non-constant operands. The (potentially vector) types to use for each of

  /// argument are passes via Tys.

  InstructionCost

  getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,

                                   ArrayRef<Type *> Tys,

                                   TTI::TargetCostKind CostKind) const;

  /// If target has efficient vector element load/store instructions, it can

  /// return true here so that insertion/extraction costs are not added to

  /// the scalarization cost of a load/store.

  bool supportsEfficientVectorElementLoadStore() const;

  /// If the target supports tail calls.

  bool supportsTailCalls() const;

  /// If target supports tail call on \p CB

  bool supportsTailCallFor(const CallBase *CB) const;

  /// Don't restrict interleaved unrolling to small loops.

  bool enableAggressiveInterleaving(bool LoopHasReductions) const;

  /// Returns options for expansion of memcmp. IsZeroCmp is

  // true if this is the expansion of memcmp(p1, p2, s) == 0.

  struct MemCmpExpansionOptions {

    // Return true if memcmp expansion is enabled.

    operator bool() const { return MaxNumLoads > 0; }

    // Maximum number of load operations.

    unsigned MaxNumLoads = 0;

    // The list of available load sizes (in bytes), sorted in decreasing order.

    SmallVector<unsigned, 8> LoadSizes;

    // For memcmp expansion when the memcmp result is only compared equal or

    // not-equal to 0, allow up to this number of load pairs per block. As an

    // example, this may allow 'memcmp(a, b, 3) == 0' in a single block:

    //   a0 = load2bytes &a[0]

    //   b0 = load2bytes &b[0]

    //   a2 = load1byte  &a[2]

    //   b2 = load1byte  &b[2]

    //   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0

    unsigned NumLoadsPerBlock = 1;

    // Set to true to allow overlapping loads. For example, 7-byte compares can

    // be done with two 4-byte compares instead of 4+2+1-byte compares. This

    // requires all loads in LoadSizes to be doable in an unaligned way.

    bool AllowOverlappingLoads = false;

  };

  MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,

                                               bool IsZeroCmp) const;

  /// Should the Select Optimization pass be enabled and ran.

  bool enableSelectOptimize() const;

  /// Enable matching of interleaved access groups.

  bool enableInterleavedAccessVectorization() const;

  /// Enable matching of interleaved access groups that contain predicated

  /// accesses or gaps and therefore vectorized using masked

  /// vector loads/stores.

  bool enableMaskedInterleavedAccessVectorization() const;

  /// Indicate that it is potentially unsafe to automatically vectorize

  /// floating-point operations because the semantics of vector and scalar

  /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math

  /// does not support IEEE-754 denormal numbers, while depending on the

  /// platform, scalar floating-point math does.

  /// This applies to floating-point math operations and calls, not memory

  /// operations, shuffles, or casts.

  bool isFPVectorizationPotentiallyUnsafe() const;

  /// Determine if the target supports unaligned memory accesses.

  bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,

                                      unsigned AddressSpace = 0,

                                      Align Alignment = Align(1),

                                      unsigned *Fast = nullptr) const;

  /// Return hardware support for population count.

  PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;

  /// Return true if the hardware has a fast square-root instruction.

  bool haveFastSqrt(Type *Ty) const;

  /// Return true if the cost of the instruction is too high to speculatively

  /// execute and should be kept behind a branch.

  /// This normally just wraps around a getInstructionCost() call, but some

  /// targets might report a low TCK_SizeAndLatency value that is incompatible

  /// with the fixed TCC_Expensive value.

  /// NOTE: This assumes the instruction passes isSafeToSpeculativelyExecute().

  bool isExpensiveToSpeculativelyExecute(const Instruction *I) const;

  /// Return true if it is faster to check if a floating-point value is NaN

  /// (or not-NaN) versus a comparison against a constant FP zero value.

  /// Targets should override this if materializing a 0.0 for comparison is

  /// generally as cheap as checking for ordered/unordered.

  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const;

  /// Return the expected cost of supporting the floating point operation

  /// of the specified type.

  InstructionCost getFPOpCost(Type *Ty) const;

  /// Return the expected cost of materializing for the given integer

  /// immediate of the specified type.

  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,

                                TargetCostKind CostKind) const;

  /// Return the expected cost of materialization for the given integer

  /// immediate of the specified type for a given instruction. The cost can be

  /// zero if the immediate can be folded into the specified instruction.

  InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,

                                    const APInt &Imm, Type *Ty,

                                    TargetCostKind CostKind,

                                    Instruction *Inst = nullptr) const;

  InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,

                                      const APInt &Imm, Type *Ty,

                                      TargetCostKind CostKind) const;

  /// Return the expected cost for the given integer when optimising

  /// for size. This is different than the other integer immediate cost

  /// functions in that it is subtarget agnostic. This is useful when you e.g.

  /// target one ISA such as Aarch32 but smaller encodings could be possible

  /// with another such as Thumb. This return value is used as a penalty when

  /// the total costs for a constant is calculated (the bigger the cost, the

  /// more beneficial constant hoisting is).

  InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,

                                        const APInt &Imm, Type *Ty) const;

  /// @}

  /// \name Vector Target Information

  /// @{