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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_f32: |
| 2 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_s32: |
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| 3 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_u32: |
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| 4 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_f32: |
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| 5 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_s32: |
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| 6 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_u32: |
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| 7 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_f32: |
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| 8 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_s32: |
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| 9 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_u32: |
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| 10 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_f32: |
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| 11 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_s32: |
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| 12 | case ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_u32: |
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| 13 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_f32: |
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| 14 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_f32: |
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| 15 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_s32: |
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| 16 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_p_u32: |
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| 17 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_s32: |
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| 18 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_u32: |
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| 19 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_f32: |
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| 20 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_f32: |
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| 21 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_s32: |
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| 22 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_p_u32: |
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| 23 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_s32: |
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| 24 | case ARM::BI__builtin_arm_mve_vstrwq_scatter_base_wb_u32: |
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| 25 | return SemaBuiltinConstantArgRange(TheCall, 1, -0x1FC, 0x1FC) || |
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| 26 | SemaBuiltinConstantArgMultiple(TheCall, 1, 4); |
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| 27 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_s64: |
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| 28 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_u64: |
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| 29 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_s64: |
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| 30 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_u64: |
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| 31 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_s64: |
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| 32 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_u64: |
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| 33 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_s64: |
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| 34 | case ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_u64: |
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| 35 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_s64: |
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| 36 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_p_u64: |
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| 37 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_s64: |
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| 38 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_u64: |
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| 39 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_s64: |
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| 40 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_p_u64: |
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| 41 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_s64: |
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| 42 | case ARM::BI__builtin_arm_mve_vstrdq_scatter_base_wb_u64: |
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| 43 | return SemaBuiltinConstantArgRange(TheCall, 1, -0x3F8, 0x3F8) || |
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| 44 | SemaBuiltinConstantArgMultiple(TheCall, 1, 8); |
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| 45 | case ARM::BI__builtin_arm_mve_vgetq_lane_s64: |
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| 46 | case ARM::BI__builtin_arm_mve_vgetq_lane_u64: |
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| 47 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x1); |
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| 48 | case ARM::BI__builtin_arm_mve_vqshlq_n_s32: |
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| 49 | case ARM::BI__builtin_arm_mve_vqshlq_n_u32: |
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| 50 | case ARM::BI__builtin_arm_mve_vqshluq_n_s32: |
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| 51 | case ARM::BI__builtin_arm_mve_vshlq_n_s32: |
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| 52 | case ARM::BI__builtin_arm_mve_vshlq_n_u32: |
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| 53 | case ARM::BI__builtin_arm_mve_vshlq_x_n_s32: |
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| 54 | case ARM::BI__builtin_arm_mve_vshlq_x_n_u32: |
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| 55 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x1F); |
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| 56 | case ARM::BI__builtin_arm_mve_vgetq_lane_f32: |
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| 57 | case ARM::BI__builtin_arm_mve_vgetq_lane_s32: |
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| 58 | case ARM::BI__builtin_arm_mve_vgetq_lane_u32: |
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| 59 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x3); |
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| 60 | case ARM::BI__builtin_arm_mve_vgetq_lane_f16: |
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| 61 | case ARM::BI__builtin_arm_mve_vgetq_lane_s16: |
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| 62 | case ARM::BI__builtin_arm_mve_vgetq_lane_u16: |
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| 63 | case ARM::BI__builtin_arm_mve_vqshlq_n_s8: |
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| 64 | case ARM::BI__builtin_arm_mve_vqshlq_n_u8: |
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| 65 | case ARM::BI__builtin_arm_mve_vqshluq_n_s8: |
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| 66 | case ARM::BI__builtin_arm_mve_vshlq_n_s8: |
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| 67 | case ARM::BI__builtin_arm_mve_vshlq_n_u8: |
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| 68 | case ARM::BI__builtin_arm_mve_vshlq_x_n_s8: |
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| 69 | case ARM::BI__builtin_arm_mve_vshlq_x_n_u8: |
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| 70 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x7); |
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| 71 | case ARM::BI__builtin_arm_mve_vgetq_lane_s8: |
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| 72 | case ARM::BI__builtin_arm_mve_vgetq_lane_u8: |
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| 73 | case ARM::BI__builtin_arm_mve_vqshlq_n_s16: |
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| 74 | case ARM::BI__builtin_arm_mve_vqshlq_n_u16: |
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| 75 | case ARM::BI__builtin_arm_mve_vqshluq_n_s16: |
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| 76 | case ARM::BI__builtin_arm_mve_vshlq_n_s16: |
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| 77 | case ARM::BI__builtin_arm_mve_vshlq_n_u16: |
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| 78 | case ARM::BI__builtin_arm_mve_vshlq_x_n_s16: |
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| 79 | case ARM::BI__builtin_arm_mve_vshlq_x_n_u16: |
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| 80 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0xF); |
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| 81 | case ARM::BI__builtin_arm_mve_vcvtq_n_f16_s16: |
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| 82 | case ARM::BI__builtin_arm_mve_vcvtq_n_f16_u16: |
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| 83 | case ARM::BI__builtin_arm_mve_vcvtq_n_s16_f16: |
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| 84 | case ARM::BI__builtin_arm_mve_vcvtq_n_u16_f16: |
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| 85 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_s16: |
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| 86 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_u16: |
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| 87 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_s16_f16: |
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| 88 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_u16_f16: |
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| 89 | case ARM::BI__builtin_arm_mve_vrshrq_n_s16: |
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| 90 | case ARM::BI__builtin_arm_mve_vrshrq_n_u16: |
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| 91 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_s16: |
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| 92 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_u16: |
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| 93 | case ARM::BI__builtin_arm_mve_vshllbq_n_s16: |
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| 94 | case ARM::BI__builtin_arm_mve_vshllbq_n_u16: |
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| 95 | case ARM::BI__builtin_arm_mve_vshllbq_x_n_s16: |
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| 96 | case ARM::BI__builtin_arm_mve_vshllbq_x_n_u16: |
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| 97 | case ARM::BI__builtin_arm_mve_vshlltq_n_s16: |
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| 98 | case ARM::BI__builtin_arm_mve_vshlltq_n_u16: |
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| 99 | case ARM::BI__builtin_arm_mve_vshlltq_x_n_s16: |
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| 100 | case ARM::BI__builtin_arm_mve_vshlltq_x_n_u16: |
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| 101 | case ARM::BI__builtin_arm_mve_vshrq_n_s16: |
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| 102 | case ARM::BI__builtin_arm_mve_vshrq_n_u16: |
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| 103 | case ARM::BI__builtin_arm_mve_vshrq_x_n_s16: |
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| 104 | case ARM::BI__builtin_arm_mve_vshrq_x_n_u16: |
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| 105 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x1, 0x10); |
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| 106 | case ARM::BI__builtin_arm_mve_sqshl: |
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| 107 | case ARM::BI__builtin_arm_mve_sqshll: |
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| 108 | case ARM::BI__builtin_arm_mve_srshr: |
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| 109 | case ARM::BI__builtin_arm_mve_srshrl: |
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| 110 | case ARM::BI__builtin_arm_mve_uqshl: |
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| 111 | case ARM::BI__builtin_arm_mve_uqshll: |
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| 112 | case ARM::BI__builtin_arm_mve_urshr: |
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| 113 | case ARM::BI__builtin_arm_mve_urshrl: |
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| 114 | case ARM::BI__builtin_arm_mve_vcvtq_n_f32_s32: |
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| 115 | case ARM::BI__builtin_arm_mve_vcvtq_n_f32_u32: |
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| 116 | case ARM::BI__builtin_arm_mve_vcvtq_n_s32_f32: |
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| 117 | case ARM::BI__builtin_arm_mve_vcvtq_n_u32_f32: |
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| 118 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_s32: |
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| 119 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_u32: |
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| 120 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_s32_f32: |
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| 121 | case ARM::BI__builtin_arm_mve_vcvtq_x_n_u32_f32: |
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| 122 | case ARM::BI__builtin_arm_mve_vrshrq_n_s32: |
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| 123 | case ARM::BI__builtin_arm_mve_vrshrq_n_u32: |
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| 124 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_s32: |
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| 125 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_u32: |
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| 126 | case ARM::BI__builtin_arm_mve_vshrq_n_s32: |
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| 127 | case ARM::BI__builtin_arm_mve_vshrq_n_u32: |
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| 128 | case ARM::BI__builtin_arm_mve_vshrq_x_n_s32: |
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| 129 | case ARM::BI__builtin_arm_mve_vshrq_x_n_u32: |
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| 130 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x1, 0x20); |
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| 131 | case ARM::BI__builtin_arm_mve_vddupq_n_u16: |
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| 132 | case ARM::BI__builtin_arm_mve_vddupq_n_u32: |
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| 133 | case ARM::BI__builtin_arm_mve_vddupq_n_u8: |
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| 134 | case ARM::BI__builtin_arm_mve_vddupq_wb_u16: |
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| 135 | case ARM::BI__builtin_arm_mve_vddupq_wb_u32: |
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| 136 | case ARM::BI__builtin_arm_mve_vddupq_wb_u8: |
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| 137 | case ARM::BI__builtin_arm_mve_vddupq_x_n_u16: |
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| 138 | case ARM::BI__builtin_arm_mve_vddupq_x_n_u32: |
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| 139 | case ARM::BI__builtin_arm_mve_vddupq_x_n_u8: |
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| 140 | case ARM::BI__builtin_arm_mve_vddupq_x_wb_u16: |
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| 141 | case ARM::BI__builtin_arm_mve_vddupq_x_wb_u32: |
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| 142 | case ARM::BI__builtin_arm_mve_vddupq_x_wb_u8: |
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| 143 | case ARM::BI__builtin_arm_mve_vidupq_n_u16: |
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| 144 | case ARM::BI__builtin_arm_mve_vidupq_n_u32: |
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| 145 | case ARM::BI__builtin_arm_mve_vidupq_n_u8: |
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| 146 | case ARM::BI__builtin_arm_mve_vidupq_wb_u16: |
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| 147 | case ARM::BI__builtin_arm_mve_vidupq_wb_u32: |
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| 148 | case ARM::BI__builtin_arm_mve_vidupq_wb_u8: |
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| 149 | case ARM::BI__builtin_arm_mve_vidupq_x_n_u16: |
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| 150 | case ARM::BI__builtin_arm_mve_vidupq_x_n_u32: |
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| 151 | case ARM::BI__builtin_arm_mve_vidupq_x_n_u8: |
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| 152 | case ARM::BI__builtin_arm_mve_vidupq_x_wb_u16: |
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| 153 | case ARM::BI__builtin_arm_mve_vidupq_x_wb_u32: |
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| 154 | case ARM::BI__builtin_arm_mve_vidupq_x_wb_u8: |
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| 155 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x1, 0x8) || |
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| 156 | SemaBuiltinConstantArgPower2(TheCall, 1); |
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| 157 | case ARM::BI__builtin_arm_mve_vrshrq_n_s8: |
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| 158 | case ARM::BI__builtin_arm_mve_vrshrq_n_u8: |
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| 159 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_s8: |
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| 160 | case ARM::BI__builtin_arm_mve_vrshrq_x_n_u8: |
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| 161 | case ARM::BI__builtin_arm_mve_vshllbq_n_s8: |
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| 162 | case ARM::BI__builtin_arm_mve_vshllbq_n_u8: |
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| 163 | case ARM::BI__builtin_arm_mve_vshllbq_x_n_s8: |
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| 164 | case ARM::BI__builtin_arm_mve_vshllbq_x_n_u8: |
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| 165 | case ARM::BI__builtin_arm_mve_vshlltq_n_s8: |
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| 166 | case ARM::BI__builtin_arm_mve_vshlltq_n_u8: |
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| 167 | case ARM::BI__builtin_arm_mve_vshlltq_x_n_s8: |
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| 168 | case ARM::BI__builtin_arm_mve_vshlltq_x_n_u8: |
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| 169 | case ARM::BI__builtin_arm_mve_vshrq_n_s8: |
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| 170 | case ARM::BI__builtin_arm_mve_vshrq_n_u8: |
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| 171 | case ARM::BI__builtin_arm_mve_vshrq_x_n_s8: |
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| 172 | case ARM::BI__builtin_arm_mve_vshrq_x_n_u8: |
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| 173 | return SemaBuiltinConstantArgRange(TheCall, 1, 0x1, 0x8); |
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| 174 | case ARM::BI__builtin_arm_mve_vsetq_lane_s64: |
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| 175 | case ARM::BI__builtin_arm_mve_vsetq_lane_u64: |
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| 176 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x1); |
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| 177 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_s32: |
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| 178 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_u32: |
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| 179 | case ARM::BI__builtin_arm_mve_vqshluq_m_n_s32: |
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| 180 | case ARM::BI__builtin_arm_mve_vshlq_m_n_s32: |
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| 181 | case ARM::BI__builtin_arm_mve_vshlq_m_n_u32: |
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| 182 | case ARM::BI__builtin_arm_mve_vsliq_m_n_s32: |
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| 183 | case ARM::BI__builtin_arm_mve_vsliq_m_n_u32: |
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| 184 | case ARM::BI__builtin_arm_mve_vsliq_n_s32: |
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| 185 | case ARM::BI__builtin_arm_mve_vsliq_n_u32: |
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| 186 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x1F); |
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| 187 | case ARM::BI__builtin_arm_mve_vsetq_lane_f32: |
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| 188 | case ARM::BI__builtin_arm_mve_vsetq_lane_s32: |
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| 189 | case ARM::BI__builtin_arm_mve_vsetq_lane_u32: |
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| 190 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x3); |
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| 191 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_s8: |
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| 192 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_u8: |
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| 193 | case ARM::BI__builtin_arm_mve_vqshluq_m_n_s8: |
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| 194 | case ARM::BI__builtin_arm_mve_vsetq_lane_f16: |
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| 195 | case ARM::BI__builtin_arm_mve_vsetq_lane_s16: |
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| 196 | case ARM::BI__builtin_arm_mve_vsetq_lane_u16: |
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| 197 | case ARM::BI__builtin_arm_mve_vshlq_m_n_s8: |
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| 198 | case ARM::BI__builtin_arm_mve_vshlq_m_n_u8: |
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| 199 | case ARM::BI__builtin_arm_mve_vsliq_m_n_s8: |
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| 200 | case ARM::BI__builtin_arm_mve_vsliq_m_n_u8: |
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| 201 | case ARM::BI__builtin_arm_mve_vsliq_n_s8: |
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| 202 | case ARM::BI__builtin_arm_mve_vsliq_n_u8: |
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| 203 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x7); |
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| 204 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_s16: |
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| 205 | case ARM::BI__builtin_arm_mve_vqshlq_m_n_u16: |
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| 206 | case ARM::BI__builtin_arm_mve_vqshluq_m_n_s16: |
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| 207 | case ARM::BI__builtin_arm_mve_vsetq_lane_s8: |
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| 208 | case ARM::BI__builtin_arm_mve_vsetq_lane_u8: |
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| 209 | case ARM::BI__builtin_arm_mve_vshlq_m_n_s16: |
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| 210 | case ARM::BI__builtin_arm_mve_vshlq_m_n_u16: |
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| 211 | case ARM::BI__builtin_arm_mve_vsliq_m_n_s16: |
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| 212 | case ARM::BI__builtin_arm_mve_vsliq_m_n_u16: |
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| 213 | case ARM::BI__builtin_arm_mve_vsliq_n_s16: |
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| 214 | case ARM::BI__builtin_arm_mve_vsliq_n_u16: |
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| 215 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0xF); |
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| 216 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_s16: |
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| 217 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_u16: |
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| 218 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_s16_f16: |
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| 219 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_u16_f16: |
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| 220 | case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s32: |
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| 221 | case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u32: |
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| 222 | case ARM::BI__builtin_arm_mve_vqrshrnbq_n_s32: |
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| 223 | case ARM::BI__builtin_arm_mve_vqrshrnbq_n_u32: |
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| 224 | case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s32: |
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| 225 | case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u32: |
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| 226 | case ARM::BI__builtin_arm_mve_vqrshrntq_n_s32: |
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| 227 | case ARM::BI__builtin_arm_mve_vqrshrntq_n_u32: |
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| 228 | case ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s32: |
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| 229 | case ARM::BI__builtin_arm_mve_vqrshrunbq_n_s32: |
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| 230 | case ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s32: |
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| 231 | case ARM::BI__builtin_arm_mve_vqrshruntq_n_s32: |
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| 232 | case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s32: |
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| 233 | case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u32: |
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| 234 | case ARM::BI__builtin_arm_mve_vqshrnbq_n_s32: |
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| 235 | case ARM::BI__builtin_arm_mve_vqshrnbq_n_u32: |
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| 236 | case ARM::BI__builtin_arm_mve_vqshrntq_m_n_s32: |
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| 237 | case ARM::BI__builtin_arm_mve_vqshrntq_m_n_u32: |
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| 238 | case ARM::BI__builtin_arm_mve_vqshrntq_n_s32: |
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| 239 | case ARM::BI__builtin_arm_mve_vqshrntq_n_u32: |
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| 240 | case ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s32: |
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| 241 | case ARM::BI__builtin_arm_mve_vqshrunbq_n_s32: |
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| 242 | case ARM::BI__builtin_arm_mve_vqshruntq_m_n_s32: |
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| 243 | case ARM::BI__builtin_arm_mve_vqshruntq_n_s32: |
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| 244 | case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s32: |
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| 245 | case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u32: |
||
| 246 | case ARM::BI__builtin_arm_mve_vrshrnbq_n_s32: |
||
| 247 | case ARM::BI__builtin_arm_mve_vrshrnbq_n_u32: |
||
| 248 | case ARM::BI__builtin_arm_mve_vrshrntq_m_n_s32: |
||
| 249 | case ARM::BI__builtin_arm_mve_vrshrntq_m_n_u32: |
||
| 250 | case ARM::BI__builtin_arm_mve_vrshrntq_n_s32: |
||
| 251 | case ARM::BI__builtin_arm_mve_vrshrntq_n_u32: |
||
| 252 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_s16: |
||
| 253 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_u16: |
||
| 254 | case ARM::BI__builtin_arm_mve_vshllbq_m_n_s16: |
||
| 255 | case ARM::BI__builtin_arm_mve_vshllbq_m_n_u16: |
||
| 256 | case ARM::BI__builtin_arm_mve_vshlltq_m_n_s16: |
||
| 257 | case ARM::BI__builtin_arm_mve_vshlltq_m_n_u16: |
||
| 258 | case ARM::BI__builtin_arm_mve_vshrnbq_m_n_s32: |
||
| 259 | case ARM::BI__builtin_arm_mve_vshrnbq_m_n_u32: |
||
| 260 | case ARM::BI__builtin_arm_mve_vshrnbq_n_s32: |
||
| 261 | case ARM::BI__builtin_arm_mve_vshrnbq_n_u32: |
||
| 262 | case ARM::BI__builtin_arm_mve_vshrntq_m_n_s32: |
||
| 263 | case ARM::BI__builtin_arm_mve_vshrntq_m_n_u32: |
||
| 264 | case ARM::BI__builtin_arm_mve_vshrntq_n_s32: |
||
| 265 | case ARM::BI__builtin_arm_mve_vshrntq_n_u32: |
||
| 266 | case ARM::BI__builtin_arm_mve_vshrq_m_n_s16: |
||
| 267 | case ARM::BI__builtin_arm_mve_vshrq_m_n_u16: |
||
| 268 | case ARM::BI__builtin_arm_mve_vsriq_m_n_s16: |
||
| 269 | case ARM::BI__builtin_arm_mve_vsriq_m_n_u16: |
||
| 270 | case ARM::BI__builtin_arm_mve_vsriq_n_s16: |
||
| 271 | case ARM::BI__builtin_arm_mve_vsriq_n_u16: |
||
| 272 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x1, 0x10); |
||
| 273 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_s32: |
||
| 274 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_u32: |
||
| 275 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_s32_f32: |
||
| 276 | case ARM::BI__builtin_arm_mve_vcvtq_m_n_u32_f32: |
||
| 277 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_s32: |
||
| 278 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_u32: |
||
| 279 | case ARM::BI__builtin_arm_mve_vshlcq_m_s16: |
||
| 280 | case ARM::BI__builtin_arm_mve_vshlcq_m_s32: |
||
| 281 | case ARM::BI__builtin_arm_mve_vshlcq_m_s8: |
||
| 282 | case ARM::BI__builtin_arm_mve_vshlcq_m_u16: |
||
| 283 | case ARM::BI__builtin_arm_mve_vshlcq_m_u32: |
||
| 284 | case ARM::BI__builtin_arm_mve_vshlcq_m_u8: |
||
| 285 | case ARM::BI__builtin_arm_mve_vshlcq_s16: |
||
| 286 | case ARM::BI__builtin_arm_mve_vshlcq_s32: |
||
| 287 | case ARM::BI__builtin_arm_mve_vshlcq_s8: |
||
| 288 | case ARM::BI__builtin_arm_mve_vshlcq_u16: |
||
| 289 | case ARM::BI__builtin_arm_mve_vshlcq_u32: |
||
| 290 | case ARM::BI__builtin_arm_mve_vshlcq_u8: |
||
| 291 | case ARM::BI__builtin_arm_mve_vshrq_m_n_s32: |
||
| 292 | case ARM::BI__builtin_arm_mve_vshrq_m_n_u32: |
||
| 293 | case ARM::BI__builtin_arm_mve_vsriq_m_n_s32: |
||
| 294 | case ARM::BI__builtin_arm_mve_vsriq_m_n_u32: |
||
| 295 | case ARM::BI__builtin_arm_mve_vsriq_n_s32: |
||
| 296 | case ARM::BI__builtin_arm_mve_vsriq_n_u32: |
||
| 297 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x1, 0x20); |
||
| 298 | case ARM::BI__builtin_arm_mve_vddupq_m_n_u16: |
||
| 299 | case ARM::BI__builtin_arm_mve_vddupq_m_n_u32: |
||
| 300 | case ARM::BI__builtin_arm_mve_vddupq_m_n_u8: |
||
| 301 | case ARM::BI__builtin_arm_mve_vddupq_m_wb_u16: |
||
| 302 | case ARM::BI__builtin_arm_mve_vddupq_m_wb_u32: |
||
| 303 | case ARM::BI__builtin_arm_mve_vddupq_m_wb_u8: |
||
| 304 | case ARM::BI__builtin_arm_mve_vdwdupq_n_u16: |
||
| 305 | case ARM::BI__builtin_arm_mve_vdwdupq_n_u32: |
||
| 306 | case ARM::BI__builtin_arm_mve_vdwdupq_n_u8: |
||
| 307 | case ARM::BI__builtin_arm_mve_vdwdupq_wb_u16: |
||
| 308 | case ARM::BI__builtin_arm_mve_vdwdupq_wb_u32: |
||
| 309 | case ARM::BI__builtin_arm_mve_vdwdupq_wb_u8: |
||
| 310 | case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u16: |
||
| 311 | case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u32: |
||
| 312 | case ARM::BI__builtin_arm_mve_vdwdupq_x_n_u8: |
||
| 313 | case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u16: |
||
| 314 | case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u32: |
||
| 315 | case ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u8: |
||
| 316 | case ARM::BI__builtin_arm_mve_vidupq_m_n_u16: |
||
| 317 | case ARM::BI__builtin_arm_mve_vidupq_m_n_u32: |
||
| 318 | case ARM::BI__builtin_arm_mve_vidupq_m_n_u8: |
||
| 319 | case ARM::BI__builtin_arm_mve_vidupq_m_wb_u16: |
||
| 320 | case ARM::BI__builtin_arm_mve_vidupq_m_wb_u32: |
||
| 321 | case ARM::BI__builtin_arm_mve_vidupq_m_wb_u8: |
||
| 322 | case ARM::BI__builtin_arm_mve_viwdupq_n_u16: |
||
| 323 | case ARM::BI__builtin_arm_mve_viwdupq_n_u32: |
||
| 324 | case ARM::BI__builtin_arm_mve_viwdupq_n_u8: |
||
| 325 | case ARM::BI__builtin_arm_mve_viwdupq_wb_u16: |
||
| 326 | case ARM::BI__builtin_arm_mve_viwdupq_wb_u32: |
||
| 327 | case ARM::BI__builtin_arm_mve_viwdupq_wb_u8: |
||
| 328 | case ARM::BI__builtin_arm_mve_viwdupq_x_n_u16: |
||
| 329 | case ARM::BI__builtin_arm_mve_viwdupq_x_n_u32: |
||
| 330 | case ARM::BI__builtin_arm_mve_viwdupq_x_n_u8: |
||
| 331 | case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u16: |
||
| 332 | case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u32: |
||
| 333 | case ARM::BI__builtin_arm_mve_viwdupq_x_wb_u8: |
||
| 334 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x1, 0x8) || |
||
| 335 | SemaBuiltinConstantArgPower2(TheCall, 2); |
||
| 336 | case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_s16: |
||
| 337 | case ARM::BI__builtin_arm_mve_vqrshrnbq_m_n_u16: |
||
| 338 | case ARM::BI__builtin_arm_mve_vqrshrnbq_n_s16: |
||
| 339 | case ARM::BI__builtin_arm_mve_vqrshrnbq_n_u16: |
||
| 340 | case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_s16: |
||
| 341 | case ARM::BI__builtin_arm_mve_vqrshrntq_m_n_u16: |
||
| 342 | case ARM::BI__builtin_arm_mve_vqrshrntq_n_s16: |
||
| 343 | case ARM::BI__builtin_arm_mve_vqrshrntq_n_u16: |
||
| 344 | case ARM::BI__builtin_arm_mve_vqrshrunbq_m_n_s16: |
||
| 345 | case ARM::BI__builtin_arm_mve_vqrshrunbq_n_s16: |
||
| 346 | case ARM::BI__builtin_arm_mve_vqrshruntq_m_n_s16: |
||
| 347 | case ARM::BI__builtin_arm_mve_vqrshruntq_n_s16: |
||
| 348 | case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_s16: |
||
| 349 | case ARM::BI__builtin_arm_mve_vqshrnbq_m_n_u16: |
||
| 350 | case ARM::BI__builtin_arm_mve_vqshrnbq_n_s16: |
||
| 351 | case ARM::BI__builtin_arm_mve_vqshrnbq_n_u16: |
||
| 352 | case ARM::BI__builtin_arm_mve_vqshrntq_m_n_s16: |
||
| 353 | case ARM::BI__builtin_arm_mve_vqshrntq_m_n_u16: |
||
| 354 | case ARM::BI__builtin_arm_mve_vqshrntq_n_s16: |
||
| 355 | case ARM::BI__builtin_arm_mve_vqshrntq_n_u16: |
||
| 356 | case ARM::BI__builtin_arm_mve_vqshrunbq_m_n_s16: |
||
| 357 | case ARM::BI__builtin_arm_mve_vqshrunbq_n_s16: |
||
| 358 | case ARM::BI__builtin_arm_mve_vqshruntq_m_n_s16: |
||
| 359 | case ARM::BI__builtin_arm_mve_vqshruntq_n_s16: |
||
| 360 | case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_s16: |
||
| 361 | case ARM::BI__builtin_arm_mve_vrshrnbq_m_n_u16: |
||
| 362 | case ARM::BI__builtin_arm_mve_vrshrnbq_n_s16: |
||
| 363 | case ARM::BI__builtin_arm_mve_vrshrnbq_n_u16: |
||
| 364 | case ARM::BI__builtin_arm_mve_vrshrntq_m_n_s16: |
||
| 365 | case ARM::BI__builtin_arm_mve_vrshrntq_m_n_u16: |
||
| 366 | case ARM::BI__builtin_arm_mve_vrshrntq_n_s16: |
||
| 367 | case ARM::BI__builtin_arm_mve_vrshrntq_n_u16: |
||
| 368 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_s8: |
||
| 369 | case ARM::BI__builtin_arm_mve_vrshrq_m_n_u8: |
||
| 370 | case ARM::BI__builtin_arm_mve_vshllbq_m_n_s8: |
||
| 371 | case ARM::BI__builtin_arm_mve_vshllbq_m_n_u8: |
||
| 372 | case ARM::BI__builtin_arm_mve_vshlltq_m_n_s8: |
||
| 373 | case ARM::BI__builtin_arm_mve_vshlltq_m_n_u8: |
||
| 374 | case ARM::BI__builtin_arm_mve_vshrnbq_m_n_s16: |
||
| 375 | case ARM::BI__builtin_arm_mve_vshrnbq_m_n_u16: |
||
| 376 | case ARM::BI__builtin_arm_mve_vshrnbq_n_s16: |
||
| 377 | case ARM::BI__builtin_arm_mve_vshrnbq_n_u16: |
||
| 378 | case ARM::BI__builtin_arm_mve_vshrntq_m_n_s16: |
||
| 379 | case ARM::BI__builtin_arm_mve_vshrntq_m_n_u16: |
||
| 380 | case ARM::BI__builtin_arm_mve_vshrntq_n_s16: |
||
| 381 | case ARM::BI__builtin_arm_mve_vshrntq_n_u16: |
||
| 382 | case ARM::BI__builtin_arm_mve_vshrq_m_n_s8: |
||
| 383 | case ARM::BI__builtin_arm_mve_vshrq_m_n_u8: |
||
| 384 | case ARM::BI__builtin_arm_mve_vsriq_m_n_s8: |
||
| 385 | case ARM::BI__builtin_arm_mve_vsriq_m_n_u8: |
||
| 386 | case ARM::BI__builtin_arm_mve_vsriq_n_s8: |
||
| 387 | case ARM::BI__builtin_arm_mve_vsriq_n_u8: |
||
| 388 | return SemaBuiltinConstantArgRange(TheCall, 2, 0x1, 0x8); |
||
| 389 | case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u16: |
||
| 390 | case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u32: |
||
| 391 | case ARM::BI__builtin_arm_mve_vdwdupq_m_n_u8: |
||
| 392 | case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u16: |
||
| 393 | case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u32: |
||
| 394 | case ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u8: |
||
| 395 | case ARM::BI__builtin_arm_mve_viwdupq_m_n_u16: |
||
| 396 | case ARM::BI__builtin_arm_mve_viwdupq_m_n_u32: |
||
| 397 | case ARM::BI__builtin_arm_mve_viwdupq_m_n_u8: |
||
| 398 | case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u16: |
||
| 399 | case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u32: |
||
| 400 | case ARM::BI__builtin_arm_mve_viwdupq_m_wb_u8: |
||
| 401 | return SemaBuiltinConstantArgRange(TheCall, 3, 0x1, 0x8) || |
||
| 402 | SemaBuiltinConstantArgPower2(TheCall, 3); |
||
| 403 | case ARM::BI__builtin_arm_mve_vbicq_m_n_s16: |
||
| 404 | case ARM::BI__builtin_arm_mve_vbicq_m_n_u16: |
||
| 405 | case ARM::BI__builtin_arm_mve_vbicq_n_s16: |
||
| 406 | case ARM::BI__builtin_arm_mve_vbicq_n_u16: |
||
| 407 | case ARM::BI__builtin_arm_mve_vorrq_m_n_s16: |
||
| 408 | case ARM::BI__builtin_arm_mve_vorrq_m_n_u16: |
||
| 409 | case ARM::BI__builtin_arm_mve_vorrq_n_s16: |
||
| 410 | case ARM::BI__builtin_arm_mve_vorrq_n_u16: |
||
| 411 | return SemaBuiltinConstantArgShiftedByte(TheCall, 1, 16); |
||
| 412 | case ARM::BI__builtin_arm_mve_vbicq_m_n_s32: |
||
| 413 | case ARM::BI__builtin_arm_mve_vbicq_m_n_u32: |
||
| 414 | case ARM::BI__builtin_arm_mve_vbicq_n_s32: |
||
| 415 | case ARM::BI__builtin_arm_mve_vbicq_n_u32: |
||
| 416 | case ARM::BI__builtin_arm_mve_vorrq_m_n_s32: |
||
| 417 | case ARM::BI__builtin_arm_mve_vorrq_m_n_u32: |
||
| 418 | case ARM::BI__builtin_arm_mve_vorrq_n_s32: |
||
| 419 | case ARM::BI__builtin_arm_mve_vorrq_n_u32: |
||
| 420 | return SemaBuiltinConstantArgShiftedByte(TheCall, 1, 32); |
||
| 421 | case ARM::BI__builtin_arm_mve_vmvnq_n_s16: |
||
| 422 | case ARM::BI__builtin_arm_mve_vmvnq_n_u16: |
||
| 423 | case ARM::BI__builtin_arm_mve_vmvnq_x_n_s16: |
||
| 424 | case ARM::BI__builtin_arm_mve_vmvnq_x_n_u16: |
||
| 425 | return SemaBuiltinConstantArgShiftedByteOrXXFF(TheCall, 0, 16); |
||
| 426 | case ARM::BI__builtin_arm_mve_vmvnq_n_s32: |
||
| 427 | case ARM::BI__builtin_arm_mve_vmvnq_n_u32: |
||
| 428 | case ARM::BI__builtin_arm_mve_vmvnq_x_n_s32: |
||
| 429 | case ARM::BI__builtin_arm_mve_vmvnq_x_n_u32: |
||
| 430 | return SemaBuiltinConstantArgShiftedByteOrXXFF(TheCall, 0, 32); |
||
| 431 | case ARM::BI__builtin_arm_mve_vmvnq_m_n_s16: |
||
| 432 | case ARM::BI__builtin_arm_mve_vmvnq_m_n_u16: |
||
| 433 | return SemaBuiltinConstantArgShiftedByteOrXXFF(TheCall, 1, 16); |
||
| 434 | case ARM::BI__builtin_arm_mve_vmvnq_m_n_s32: |
||
| 435 | case ARM::BI__builtin_arm_mve_vmvnq_m_n_u32: |
||
| 436 | return SemaBuiltinConstantArgShiftedByteOrXXFF(TheCall, 1, 32); |