Subversion Repositories QNX 8.QNX8 LLVM/Clang compiler suite

static const IntrinToName MapData[] = {

  { ARM::BI__builtin_arm_mve_asrl, 0, -1},

  { ARM::BI__builtin_arm_mve_lsll, 5, -1},

  { ARM::BI__builtin_arm_mve_sqrshr, 10, -1},

  { ARM::BI__builtin_arm_mve_sqrshrl, 17, -1},

  { ARM::BI__builtin_arm_mve_sqrshrl_sat48, 25, -1},

  { ARM::BI__builtin_arm_mve_sqshl, 39, -1},

  { ARM::BI__builtin_arm_mve_sqshll, 45, -1},

  { ARM::BI__builtin_arm_mve_srshr, 52, -1},

  { ARM::BI__builtin_arm_mve_srshrl, 58, -1},

  { ARM::BI__builtin_arm_mve_uqrshl, 65, -1},

  { ARM::BI__builtin_arm_mve_uqrshll, 72, -1},

  { ARM::BI__builtin_arm_mve_uqrshll_sat48, 80, -1},

  { ARM::BI__builtin_arm_mve_uqshl, 94, -1},

  { ARM::BI__builtin_arm_mve_uqshll, 100, -1},

  { ARM::BI__builtin_arm_mve_urshr, 107, -1},

  { ARM::BI__builtin_arm_mve_urshrl, 113, -1},

  { ARM::BI__builtin_arm_mve_vabavq_p_s16, 129, 120},

  { ARM::BI__builtin_arm_mve_vabavq_p_s32, 142, 120},

  { ARM::BI__builtin_arm_mve_vabavq_p_s8, 155, 120},

  { ARM::BI__builtin_arm_mve_vabavq_p_u16, 167, 120},

  { ARM::BI__builtin_arm_mve_vabavq_p_u32, 180, 120},

  { ARM::BI__builtin_arm_mve_vabavq_p_u8, 193, 120},

  { ARM::BI__builtin_arm_mve_vabavq_s16, 212, 205},

  { ARM::BI__builtin_arm_mve_vabavq_s32, 223, 205},

  { ARM::BI__builtin_arm_mve_vabavq_s8, 234, 205},

  { ARM::BI__builtin_arm_mve_vabavq_u16, 244, 205},

  { ARM::BI__builtin_arm_mve_vabavq_u32, 255, 205},

  { ARM::BI__builtin_arm_mve_vabavq_u8, 266, 205},

  { ARM::BI__builtin_arm_mve_vabdq_f16, 282, 276},

  { ARM::BI__builtin_arm_mve_vabdq_f32, 292, 276},

  { ARM::BI__builtin_arm_mve_vabdq_m_f16, 310, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_f32, 322, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_s16, 334, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_s32, 346, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_s8, 358, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_u16, 369, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_u32, 381, 302},

  { ARM::BI__builtin_arm_mve_vabdq_m_u8, 393, 302},

  { ARM::BI__builtin_arm_mve_vabdq_s16, 404, 276},

  { ARM::BI__builtin_arm_mve_vabdq_s32, 414, 276},

  { ARM::BI__builtin_arm_mve_vabdq_s8, 424, 276},

  { ARM::BI__builtin_arm_mve_vabdq_u16, 433, 276},

  { ARM::BI__builtin_arm_mve_vabdq_u32, 443, 276},

  { ARM::BI__builtin_arm_mve_vabdq_u8, 453, 276},

  { ARM::BI__builtin_arm_mve_vabdq_x_f16, 470, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_f32, 482, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_s16, 494, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_s32, 506, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_s8, 518, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_u16, 529, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_u32, 541, 462},

  { ARM::BI__builtin_arm_mve_vabdq_x_u8, 553, 462},

  { ARM::BI__builtin_arm_mve_vabsq_f16, 570, 564},

  { ARM::BI__builtin_arm_mve_vabsq_f32, 580, 564},

  { ARM::BI__builtin_arm_mve_vabsq_m_f16, 598, 590},

  { ARM::BI__builtin_arm_mve_vabsq_m_f32, 610, 590},

  { ARM::BI__builtin_arm_mve_vabsq_m_s16, 622, 590},

  { ARM::BI__builtin_arm_mve_vabsq_m_s32, 634, 590},

  { ARM::BI__builtin_arm_mve_vabsq_m_s8, 646, 590},

  { ARM::BI__builtin_arm_mve_vabsq_s16, 657, 564},

  { ARM::BI__builtin_arm_mve_vabsq_s32, 667, 564},

  { ARM::BI__builtin_arm_mve_vabsq_s8, 677, 564},

  { ARM::BI__builtin_arm_mve_vabsq_x_f16, 694, 686},

  { ARM::BI__builtin_arm_mve_vabsq_x_f32, 706, 686},

  { ARM::BI__builtin_arm_mve_vabsq_x_s16, 718, 686},

  { ARM::BI__builtin_arm_mve_vabsq_x_s32, 730, 686},

  { ARM::BI__builtin_arm_mve_vabsq_x_s8, 742, 686},

  { ARM::BI__builtin_arm_mve_vadciq_m_s32, 762, 753},

  { ARM::BI__builtin_arm_mve_vadciq_m_u32, 775, 753},

  { ARM::BI__builtin_arm_mve_vadciq_s32, 795, 788},

  { ARM::BI__builtin_arm_mve_vadciq_u32, 806, 788},

  { ARM::BI__builtin_arm_mve_vadcq_m_s32, 825, 817},

  { ARM::BI__builtin_arm_mve_vadcq_m_u32, 837, 817},

  { ARM::BI__builtin_arm_mve_vadcq_s32, 855, 849},

  { ARM::BI__builtin_arm_mve_vadcq_u32, 865, 849},

  { ARM::BI__builtin_arm_mve_vaddlvaq_p_s32, 886, 875},

  { ARM::BI__builtin_arm_mve_vaddlvaq_p_u32, 901, 875},

  { ARM::BI__builtin_arm_mve_vaddlvaq_s32, 925, 916},

  { ARM::BI__builtin_arm_mve_vaddlvaq_u32, 938, 916},

  { ARM::BI__builtin_arm_mve_vaddlvq_p_s32, 961, 951},

  { ARM::BI__builtin_arm_mve_vaddlvq_p_u32, 975, 951},

  { ARM::BI__builtin_arm_mve_vaddlvq_s32, 997, 989},

  { ARM::BI__builtin_arm_mve_vaddlvq_u32, 1009, 989},

  { ARM::BI__builtin_arm_mve_vaddq_f16, 1027, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_f32, 1037, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_m_f16, 1055, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_f32, 1067, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_f16, 1079, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_f32, 1093, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_s16, 1107, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_s32, 1121, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_s8, 1135, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_u16, 1148, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_u32, 1162, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_n_u8, 1176, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_s16, 1189, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_s32, 1201, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_s8, 1213, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_u16, 1224, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_u32, 1236, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_m_u8, 1248, 1047},

  { ARM::BI__builtin_arm_mve_vaddq_n_f16, 1259, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_f32, 1271, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_s16, 1283, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_s32, 1295, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_s8, 1307, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_u16, 1318, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_u32, 1330, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_n_u8, 1342, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_s16, 1353, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_s32, 1363, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_s8, 1373, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_u16, 1382, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_u32, 1392, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_u8, 1402, 1021},

  { ARM::BI__builtin_arm_mve_vaddq_x_f16, 1419, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_f32, 1431, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_f16, 1443, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_f32, 1457, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_s16, 1471, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_s32, 1485, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_s8, 1499, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_u16, 1512, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_u32, 1526, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_n_u8, 1540, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_s16, 1553, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_s32, 1565, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_s8, 1577, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_u16, 1588, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_u32, 1600, 1411},

  { ARM::BI__builtin_arm_mve_vaddq_x_u8, 1612, 1411},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_s16, 1633, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_s32, 1647, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_s8, 1661, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_u16, 1674, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_u32, 1688, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_p_u8, 1702, 1623},

  { ARM::BI__builtin_arm_mve_vaddvaq_s16, 1723, 1715},

  { ARM::BI__builtin_arm_mve_vaddvaq_s32, 1735, 1715},

  { ARM::BI__builtin_arm_mve_vaddvaq_s8, 1747, 1715},

  { ARM::BI__builtin_arm_mve_vaddvaq_u16, 1758, 1715},

  { ARM::BI__builtin_arm_mve_vaddvaq_u32, 1770, 1715},

  { ARM::BI__builtin_arm_mve_vaddvaq_u8, 1782, 1715},

  { ARM::BI__builtin_arm_mve_vaddvq_p_s16, 1802, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_p_s32, 1815, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_p_s8, 1828, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_p_u16, 1840, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_p_u32, 1853, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_p_u8, 1866, 1793},

  { ARM::BI__builtin_arm_mve_vaddvq_s16, 1885, 1878},

  { ARM::BI__builtin_arm_mve_vaddvq_s32, 1896, 1878},

  { ARM::BI__builtin_arm_mve_vaddvq_s8, 1907, 1878},

  { ARM::BI__builtin_arm_mve_vaddvq_u16, 1917, 1878},

  { ARM::BI__builtin_arm_mve_vaddvq_u32, 1928, 1878},

  { ARM::BI__builtin_arm_mve_vaddvq_u8, 1939, 1878},

  { ARM::BI__builtin_arm_mve_vandq_f16, 1955, 1949},

  { ARM::BI__builtin_arm_mve_vandq_f32, 1965, 1949},

  { ARM::BI__builtin_arm_mve_vandq_m_f16, 1983, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_f32, 1995, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_s16, 2007, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_s32, 2019, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_s8, 2031, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_u16, 2042, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_u32, 2054, 1975},

  { ARM::BI__builtin_arm_mve_vandq_m_u8, 2066, 1975},

  { ARM::BI__builtin_arm_mve_vandq_s16, 2077, 1949},

  { ARM::BI__builtin_arm_mve_vandq_s32, 2087, 1949},

  { ARM::BI__builtin_arm_mve_vandq_s8, 2097, 1949},

  { ARM::BI__builtin_arm_mve_vandq_u16, 2106, 1949},

  { ARM::BI__builtin_arm_mve_vandq_u32, 2116, 1949},

  { ARM::BI__builtin_arm_mve_vandq_u8, 2126, 1949},

  { ARM::BI__builtin_arm_mve_vandq_x_f16, 2143, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_f32, 2155, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_s16, 2167, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_s32, 2179, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_s8, 2191, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_u16, 2202, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_u32, 2214, 2135},

  { ARM::BI__builtin_arm_mve_vandq_x_u8, 2226, 2135},

  { ARM::BI__builtin_arm_mve_vbicq_f16, 2243, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_f32, 2253, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_m_f16, 2271, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_f32, 2283, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_n_s16, 2305, 2295},

  { ARM::BI__builtin_arm_mve_vbicq_m_n_s32, 2319, 2295},

  { ARM::BI__builtin_arm_mve_vbicq_m_n_u16, 2333, 2295},

  { ARM::BI__builtin_arm_mve_vbicq_m_n_u32, 2347, 2295},

  { ARM::BI__builtin_arm_mve_vbicq_m_s16, 2361, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_s32, 2373, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_s8, 2385, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_u16, 2396, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_u32, 2408, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_m_u8, 2420, 2263},

  { ARM::BI__builtin_arm_mve_vbicq_n_s16, 2431, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_n_s32, 2443, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_n_u16, 2455, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_n_u32, 2467, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_s16, 2479, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_s32, 2489, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_s8, 2499, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_u16, 2508, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_u32, 2518, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_u8, 2528, 2237},

  { ARM::BI__builtin_arm_mve_vbicq_x_f16, 2545, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_f32, 2557, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_s16, 2569, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_s32, 2581, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_s8, 2593, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_u16, 2604, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_u32, 2616, 2537},

  { ARM::BI__builtin_arm_mve_vbicq_x_u8, 2628, 2537},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_f16, 2648, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_f32, 2663, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s16, 2678, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s32, 2693, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_s8, 2708, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u16, 2722, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u32, 2737, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_m_n_u8, 2752, 2639},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_f16, 2773, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_f32, 2786, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_s16, 2799, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_s32, 2812, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_s8, 2825, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_u16, 2837, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_u32, 2850, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_n_u8, 2863, 2766},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_f16, 2884, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_f32, 2899, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s16, 2914, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s32, 2929, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_s8, 2944, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u16, 2958, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u32, 2973, 2875},

  { ARM::BI__builtin_arm_mve_vbrsrq_x_n_u8, 2988, 2875},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_f16, 3016, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_f32, 3034, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_f16, 3068, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_f32, 3088, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s16, 3108, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s32, 3128, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_s8, 3148, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u16, 3167, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u32, 3187, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_m_u8, 3207, 3052},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_s16, 3226, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_s32, 3244, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_s8, 3262, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_u16, 3279, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_u32, 3297, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_u8, 3315, 3002},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_f16, 3348, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_f32, 3368, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s16, 3388, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s32, 3408, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_s8, 3428, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u16, 3447, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u32, 3467, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot270_x_u8, 3487, 3332},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_f16, 3519, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_f32, 3536, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_f16, 3568, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_f32, 3587, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s16, 3606, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s32, 3625, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_s8, 3644, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u16, 3662, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u32, 3681, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_m_u8, 3700, 3553},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_s16, 3718, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_s32, 3735, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_s8, 3752, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_u16, 3768, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_u32, 3785, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_u8, 3802, 3506},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_f16, 3833, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_f32, 3852, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s16, 3871, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s32, 3890, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_s8, 3909, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u16, 3927, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u32, 3946, 3818},

  { ARM::BI__builtin_arm_mve_vcaddq_rot90_x_u8, 3965, 3818},

  { ARM::BI__builtin_arm_mve_vclsq_m_s16, 3991, 3983},

  { ARM::BI__builtin_arm_mve_vclsq_m_s32, 4003, 3983},

  { ARM::BI__builtin_arm_mve_vclsq_m_s8, 4015, 3983},

  { ARM::BI__builtin_arm_mve_vclsq_s16, 4032, 4026},

  { ARM::BI__builtin_arm_mve_vclsq_s32, 4042, 4026},

  { ARM::BI__builtin_arm_mve_vclsq_s8, 4052, 4026},

  { ARM::BI__builtin_arm_mve_vclsq_x_s16, 4069, 4061},

  { ARM::BI__builtin_arm_mve_vclsq_x_s32, 4081, 4061},

  { ARM::BI__builtin_arm_mve_vclsq_x_s8, 4093, 4061},

  { ARM::BI__builtin_arm_mve_vclzq_m_s16, 4112, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_m_s32, 4124, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_m_s8, 4136, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_m_u16, 4147, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_m_u32, 4159, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_m_u8, 4171, 4104},

  { ARM::BI__builtin_arm_mve_vclzq_s16, 4188, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_s32, 4198, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_s8, 4208, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_u16, 4217, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_u32, 4227, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_u8, 4237, 4182},

  { ARM::BI__builtin_arm_mve_vclzq_x_s16, 4254, 4246},

  { ARM::BI__builtin_arm_mve_vclzq_x_s32, 4266, 4246},

  { ARM::BI__builtin_arm_mve_vclzq_x_s8, 4278, 4246},

  { ARM::BI__builtin_arm_mve_vclzq_x_u16, 4289, 4246},

  { ARM::BI__builtin_arm_mve_vclzq_x_u32, 4301, 4246},

  { ARM::BI__builtin_arm_mve_vclzq_x_u8, 4313, 4246},

  { ARM::BI__builtin_arm_mve_vcmlaq_f16, 4331, 4324},

  { ARM::BI__builtin_arm_mve_vcmlaq_f32, 4342, 4324},

  { ARM::BI__builtin_arm_mve_vcmlaq_m_f16, 4362, 4353},

  { ARM::BI__builtin_arm_mve_vcmlaq_m_f32, 4375, 4353},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot180_f16, 4402, 4388},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot180_f32, 4420, 4388},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot180_m_f16, 4454, 4438},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot180_m_f32, 4474, 4438},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot270_f16, 4508, 4494},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot270_f32, 4526, 4494},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot270_m_f16, 4560, 4544},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot270_m_f32, 4580, 4544},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot90_f16, 4613, 4600},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot90_f32, 4630, 4600},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot90_m_f16, 4662, 4647},

  { ARM::BI__builtin_arm_mve_vcmlaq_rot90_m_f32, 4681, 4647},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u16, 4710, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u32, 4726, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_n_u8, 4742, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_u16, 4757, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_u32, 4771, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_m_u8, 4785, 4700},

  { ARM::BI__builtin_arm_mve_vcmpcsq_n_u16, 4806, 4798},

  { ARM::BI__builtin_arm_mve_vcmpcsq_n_u32, 4820, 4798},

  { ARM::BI__builtin_arm_mve_vcmpcsq_n_u8, 4834, 4798},

  { ARM::BI__builtin_arm_mve_vcmpcsq_u16, 4847, 4798},

  { ARM::BI__builtin_arm_mve_vcmpcsq_u32, 4859, 4798},

  { ARM::BI__builtin_arm_mve_vcmpcsq_u8, 4871, 4798},

  { ARM::BI__builtin_arm_mve_vcmpeqq_f16, 4890, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_f32, 4902, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_f16, 4924, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_f32, 4938, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_f16, 4952, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_f32, 4968, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s16, 4984, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s32, 5000, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_s8, 5016, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u16, 5031, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u32, 5047, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_n_u8, 5063, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_s16, 5078, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_s32, 5092, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_s8, 5106, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_u16, 5119, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_u32, 5133, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_m_u8, 5147, 4914},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_f16, 5160, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_f32, 5174, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_s16, 5188, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_s32, 5202, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_s8, 5216, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_u16, 5229, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_u32, 5243, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_n_u8, 5257, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_s16, 5270, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_s32, 5282, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_s8, 5294, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_u16, 5305, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_u32, 5317, 4882},

  { ARM::BI__builtin_arm_mve_vcmpeqq_u8, 5329, 4882},

  { ARM::BI__builtin_arm_mve_vcmpgeq_f16, 5348, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_f32, 5360, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_f16, 5382, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_f32, 5396, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_f16, 5410, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_f32, 5426, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s16, 5442, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s32, 5458, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_n_s8, 5474, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_s16, 5489, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_s32, 5503, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_m_s8, 5517, 5372},

  { ARM::BI__builtin_arm_mve_vcmpgeq_n_f16, 5530, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_n_f32, 5544, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_n_s16, 5558, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_n_s32, 5572, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_n_s8, 5586, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_s16, 5599, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_s32, 5611, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgeq_s8, 5623, 5340},

  { ARM::BI__builtin_arm_mve_vcmpgtq_f16, 5642, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_f32, 5654, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_f16, 5676, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_f32, 5690, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_f16, 5704, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_f32, 5720, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s16, 5736, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s32, 5752, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_n_s8, 5768, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_s16, 5783, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_s32, 5797, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_m_s8, 5811, 5666},

  { ARM::BI__builtin_arm_mve_vcmpgtq_n_f16, 5824, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_n_f32, 5838, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_n_s16, 5852, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_n_s32, 5866, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_n_s8, 5880, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_s16, 5893, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_s32, 5905, 5634},

  { ARM::BI__builtin_arm_mve_vcmpgtq_s8, 5917, 5634},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u16, 5938, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u32, 5954, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_n_u8, 5970, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_u16, 5985, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_u32, 5999, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_m_u8, 6013, 5928},

  { ARM::BI__builtin_arm_mve_vcmphiq_n_u16, 6034, 6026},

  { ARM::BI__builtin_arm_mve_vcmphiq_n_u32, 6048, 6026},

  { ARM::BI__builtin_arm_mve_vcmphiq_n_u8, 6062, 6026},

  { ARM::BI__builtin_arm_mve_vcmphiq_u16, 6075, 6026},

  { ARM::BI__builtin_arm_mve_vcmphiq_u32, 6087, 6026},

  { ARM::BI__builtin_arm_mve_vcmphiq_u8, 6099, 6026},

  { ARM::BI__builtin_arm_mve_vcmpleq_f16, 6118, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_f32, 6130, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_f16, 6152, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_f32, 6166, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_n_f16, 6180, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_n_f32, 6196, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s16, 6212, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s32, 6228, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_n_s8, 6244, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_s16, 6259, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_s32, 6273, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_m_s8, 6287, 6142},

  { ARM::BI__builtin_arm_mve_vcmpleq_n_f16, 6300, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_n_f32, 6314, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_n_s16, 6328, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_n_s32, 6342, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_n_s8, 6356, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_s16, 6369, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_s32, 6381, 6110},

  { ARM::BI__builtin_arm_mve_vcmpleq_s8, 6393, 6110},

  { ARM::BI__builtin_arm_mve_vcmpltq_f16, 6412, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_f32, 6424, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_f16, 6446, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_f32, 6460, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_n_f16, 6474, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_n_f32, 6490, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s16, 6506, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s32, 6522, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_n_s8, 6538, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_s16, 6553, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_s32, 6567, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_m_s8, 6581, 6436},

  { ARM::BI__builtin_arm_mve_vcmpltq_n_f16, 6594, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_n_f32, 6608, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_n_s16, 6622, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_n_s32, 6636, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_n_s8, 6650, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_s16, 6663, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_s32, 6675, 6404},

  { ARM::BI__builtin_arm_mve_vcmpltq_s8, 6687, 6404},

  { ARM::BI__builtin_arm_mve_vcmpneq_f16, 6706, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_f32, 6718, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_f16, 6740, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_f32, 6754, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_f16, 6768, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_f32, 6784, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s16, 6800, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s32, 6816, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_s8, 6832, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u16, 6847, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u32, 6863, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_n_u8, 6879, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_s16, 6894, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_s32, 6908, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_s8, 6922, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_u16, 6935, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_u32, 6949, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_m_u8, 6963, 6730},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_f16, 6976, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_f32, 6990, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_s16, 7004, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_s32, 7018, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_s8, 7032, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_u16, 7045, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_u32, 7059, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_n_u8, 7073, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_s16, 7086, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_s32, 7098, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_s8, 7110, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_u16, 7121, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_u32, 7133, 6698},

  { ARM::BI__builtin_arm_mve_vcmpneq_u8, 7145, 6698},

  { ARM::BI__builtin_arm_mve_vcmulq_f16, 7163, 7156},

  { ARM::BI__builtin_arm_mve_vcmulq_f32, 7174, 7156},

  { ARM::BI__builtin_arm_mve_vcmulq_m_f16, 7194, 7185},

  { ARM::BI__builtin_arm_mve_vcmulq_m_f32, 7207, 7185},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_f16, 7234, 7220},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_f32, 7252, 7220},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_m_f16, 7286, 7270},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_m_f32, 7306, 7270},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_x_f16, 7342, 7326},

  { ARM::BI__builtin_arm_mve_vcmulq_rot180_x_f32, 7362, 7326},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_f16, 7396, 7382},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_f32, 7414, 7382},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_m_f16, 7448, 7432},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_m_f32, 7468, 7432},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_x_f16, 7504, 7488},

  { ARM::BI__builtin_arm_mve_vcmulq_rot270_x_f32, 7524, 7488},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_f16, 7557, 7544},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_f32, 7574, 7544},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_m_f16, 7606, 7591},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_m_f32, 7625, 7591},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_x_f16, 7659, 7644},

  { ARM::BI__builtin_arm_mve_vcmulq_rot90_x_f32, 7678, 7644},

  { ARM::BI__builtin_arm_mve_vcmulq_x_f16, 7706, 7697},

  { ARM::BI__builtin_arm_mve_vcmulq_x_f32, 7719, 7697},

  { ARM::BI__builtin_arm_mve_vcreateq_f16, 7732, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_f32, 7745, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_s16, 7758, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_s32, 7771, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_s64, 7784, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_s8, 7797, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_u16, 7809, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_u32, 7822, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_u64, 7835, -1},

  { ARM::BI__builtin_arm_mve_vcreateq_u8, 7848, -1},

  { ARM::BI__builtin_arm_mve_vctp16q, 7860, -1},

  { ARM::BI__builtin_arm_mve_vctp16q_m, 7868, -1},

  { ARM::BI__builtin_arm_mve_vctp32q, 7878, -1},

  { ARM::BI__builtin_arm_mve_vctp32q_m, 7886, -1},

  { ARM::BI__builtin_arm_mve_vctp64q, 7896, -1},

  { ARM::BI__builtin_arm_mve_vctp64q_m, 7904, -1},

  { ARM::BI__builtin_arm_mve_vctp8q, 7914, -1},

  { ARM::BI__builtin_arm_mve_vctp8q_m, 7921, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_m_s16_f16, 7939, 7930},

  { ARM::BI__builtin_arm_mve_vcvtaq_m_s32_f32, 7956, 7930},

  { ARM::BI__builtin_arm_mve_vcvtaq_m_u16_f16, 7973, 7930},

  { ARM::BI__builtin_arm_mve_vcvtaq_m_u32_f32, 7990, 7930},

  { ARM::BI__builtin_arm_mve_vcvtaq_s16_f16, 8007, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_s32_f32, 8022, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_u16_f16, 8037, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_u32_f32, 8052, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_x_s16_f16, 8067, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_x_s32_f32, 8084, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_x_u16_f16, 8101, -1},

  { ARM::BI__builtin_arm_mve_vcvtaq_x_u32_f32, 8118, -1},

  { ARM::BI__builtin_arm_mve_vcvtbq_f16_f32, 8135, -1},

  { ARM::BI__builtin_arm_mve_vcvtbq_f32_f16, 8150, -1},

  { ARM::BI__builtin_arm_mve_vcvtbq_m_f16_f32, 8165, -1},

  { ARM::BI__builtin_arm_mve_vcvtbq_m_f32_f16, 8182, -1},

  { ARM::BI__builtin_arm_mve_vcvtbq_x_f32_f16, 8199, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_m_s16_f16, 8225, 8216},

  { ARM::BI__builtin_arm_mve_vcvtmq_m_s32_f32, 8242, 8216},

  { ARM::BI__builtin_arm_mve_vcvtmq_m_u16_f16, 8259, 8216},

  { ARM::BI__builtin_arm_mve_vcvtmq_m_u32_f32, 8276, 8216},

  { ARM::BI__builtin_arm_mve_vcvtmq_s16_f16, 8293, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_s32_f32, 8308, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_u16_f16, 8323, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_u32_f32, 8338, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_x_s16_f16, 8353, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_x_s32_f32, 8370, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_x_u16_f16, 8387, -1},

  { ARM::BI__builtin_arm_mve_vcvtmq_x_u32_f32, 8404, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_m_s16_f16, 8430, 8421},

  { ARM::BI__builtin_arm_mve_vcvtnq_m_s32_f32, 8447, 8421},

  { ARM::BI__builtin_arm_mve_vcvtnq_m_u16_f16, 8464, 8421},

  { ARM::BI__builtin_arm_mve_vcvtnq_m_u32_f32, 8481, 8421},

  { ARM::BI__builtin_arm_mve_vcvtnq_s16_f16, 8498, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_s32_f32, 8513, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_u16_f16, 8528, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_u32_f32, 8543, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_x_s16_f16, 8558, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_x_s32_f32, 8575, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_x_u16_f16, 8592, -1},

  { ARM::BI__builtin_arm_mve_vcvtnq_x_u32_f32, 8609, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_m_s16_f16, 8635, 8626},

  { ARM::BI__builtin_arm_mve_vcvtpq_m_s32_f32, 8652, 8626},

  { ARM::BI__builtin_arm_mve_vcvtpq_m_u16_f16, 8669, 8626},

  { ARM::BI__builtin_arm_mve_vcvtpq_m_u32_f32, 8686, 8626},

  { ARM::BI__builtin_arm_mve_vcvtpq_s16_f16, 8703, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_s32_f32, 8718, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_u16_f16, 8733, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_u32_f32, 8748, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_x_s16_f16, 8763, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_x_s32_f32, 8780, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_x_u16_f16, 8797, -1},

  { ARM::BI__builtin_arm_mve_vcvtpq_x_u32_f32, 8814, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_f16_s16, 8837, 8831},

  { ARM::BI__builtin_arm_mve_vcvtq_f16_u16, 8851, 8831},

  { ARM::BI__builtin_arm_mve_vcvtq_f32_s32, 8865, 8831},

  { ARM::BI__builtin_arm_mve_vcvtq_f32_u32, 8879, 8831},

  { ARM::BI__builtin_arm_mve_vcvtq_m_f16_s16, 8901, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_f16_u16, 8917, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_f32_s32, 8933, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_f32_u32, 8949, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_s16, 8975, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_f16_u16, 8993, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_s32, 9011, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_f32_u32, 9029, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_s16_f16, 9047, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_s32_f32, 9065, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_u16_f16, 9083, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_n_u32_f32, 9101, 8965},

  { ARM::BI__builtin_arm_mve_vcvtq_m_s16_f16, 9119, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_s32_f32, 9135, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_u16_f16, 9151, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_m_u32_f32, 9167, 8893},

  { ARM::BI__builtin_arm_mve_vcvtq_n_f16_s16, 9191, 9183},

  { ARM::BI__builtin_arm_mve_vcvtq_n_f16_u16, 9207, 9183},

  { ARM::BI__builtin_arm_mve_vcvtq_n_f32_s32, 9223, 9183},

  { ARM::BI__builtin_arm_mve_vcvtq_n_f32_u32, 9239, 9183},

  { ARM::BI__builtin_arm_mve_vcvtq_n_s16_f16, 9255, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_n_s32_f32, 9271, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_n_u16_f16, 9287, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_n_u32_f32, 9303, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_s16_f16, 9319, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_s32_f32, 9333, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_u16_f16, 9347, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_u32_f32, 9361, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_f16_s16, 9383, 9375},

  { ARM::BI__builtin_arm_mve_vcvtq_x_f16_u16, 9399, 9375},

  { ARM::BI__builtin_arm_mve_vcvtq_x_f32_s32, 9415, 9375},

  { ARM::BI__builtin_arm_mve_vcvtq_x_f32_u32, 9431, 9375},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_s16, 9457, 9447},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_f16_u16, 9475, 9447},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_s32, 9493, 9447},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_f32_u32, 9511, 9447},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_s16_f16, 9529, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_s32_f32, 9547, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_u16_f16, 9565, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_n_u32_f32, 9583, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_s16_f16, 9601, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_s32_f32, 9617, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_u16_f16, 9633, -1},

  { ARM::BI__builtin_arm_mve_vcvtq_x_u32_f32, 9649, -1},

  { ARM::BI__builtin_arm_mve_vcvttq_f16_f32, 9665, -1},

  { ARM::BI__builtin_arm_mve_vcvttq_f32_f16, 9680, -1},

  { ARM::BI__builtin_arm_mve_vcvttq_m_f16_f32, 9695, -1},

  { ARM::BI__builtin_arm_mve_vcvttq_m_f32_f16, 9712, -1},

  { ARM::BI__builtin_arm_mve_vcvttq_x_f32_f16, 9729, -1},

  { ARM::BI__builtin_arm_mve_vddupq_m_n_u16, 9755, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_m_n_u32, 9770, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_m_n_u8, 9785, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_m_wb_u16, 9799, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_m_wb_u32, 9815, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_m_wb_u8, 9831, 9746},

  { ARM::BI__builtin_arm_mve_vddupq_n_u16, 9857, 9846},

  { ARM::BI__builtin_arm_mve_vddupq_n_u32, 9881, 9870},

  { ARM::BI__builtin_arm_mve_vddupq_n_u8, 9904, 9894},

  { ARM::BI__builtin_arm_mve_vddupq_wb_u16, 9916, 9846},

  { ARM::BI__builtin_arm_mve_vddupq_wb_u32, 9930, 9870},

  { ARM::BI__builtin_arm_mve_vddupq_wb_u8, 9944, 9894},

  { ARM::BI__builtin_arm_mve_vddupq_x_n_u16, 9970, 9957},

  { ARM::BI__builtin_arm_mve_vddupq_x_n_u32, 9998, 9985},

  { ARM::BI__builtin_arm_mve_vddupq_x_n_u8, 10025, 10013},

  { ARM::BI__builtin_arm_mve_vddupq_x_wb_u16, 10039, 9957},

  { ARM::BI__builtin_arm_mve_vddupq_x_wb_u32, 10055, 9985},

  { ARM::BI__builtin_arm_mve_vddupq_x_wb_u8, 10071, 10013},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_f16, 10094, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_f32, 10108, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_s16, 10122, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_s32, 10136, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_s8, 10150, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_u16, 10163, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_u32, 10177, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_m_n_u8, 10191, 10086},

  { ARM::BI__builtin_arm_mve_vdupq_n_f16, 10204, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_f32, 10216, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_s16, 10228, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_s32, 10240, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_s8, 10252, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_u16, 10263, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_u32, 10275, -1},

  { ARM::BI__builtin_arm_mve_vdupq_n_u8, 10287, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_f16, 10298, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_f32, 10312, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_s16, 10326, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_s32, 10340, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_s8, 10354, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_u16, 10367, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_u32, 10381, -1},

  { ARM::BI__builtin_arm_mve_vdupq_x_n_u8, 10395, -1},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u16, 10418, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u32, 10434, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_n_u8, 10450, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u16, 10465, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u32, 10482, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_m_wb_u8, 10499, 10408},

  { ARM::BI__builtin_arm_mve_vdwdupq_n_u16, 10527, 10515},

  { ARM::BI__builtin_arm_mve_vdwdupq_n_u32, 10553, 10541},

  { ARM::BI__builtin_arm_mve_vdwdupq_n_u8, 10578, 10567},

  { ARM::BI__builtin_arm_mve_vdwdupq_wb_u16, 10591, 10515},

  { ARM::BI__builtin_arm_mve_vdwdupq_wb_u32, 10606, 10541},

  { ARM::BI__builtin_arm_mve_vdwdupq_wb_u8, 10621, 10567},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u16, 10649, 10635},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u32, 10679, 10665},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_n_u8, 10708, 10695},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u16, 10723, 10635},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u32, 10740, 10665},

  { ARM::BI__builtin_arm_mve_vdwdupq_x_wb_u8, 10757, 10695},

  { ARM::BI__builtin_arm_mve_veorq_f16, 10779, 10773},

  { ARM::BI__builtin_arm_mve_veorq_f32, 10789, 10773},

  { ARM::BI__builtin_arm_mve_veorq_m_f16, 10807, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_f32, 10819, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_s16, 10831, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_s32, 10843, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_s8, 10855, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_u16, 10866, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_u32, 10878, 10799},

  { ARM::BI__builtin_arm_mve_veorq_m_u8, 10890, 10799},

  { ARM::BI__builtin_arm_mve_veorq_s16, 10901, 10773},

  { ARM::BI__builtin_arm_mve_veorq_s32, 10911, 10773},

  { ARM::BI__builtin_arm_mve_veorq_s8, 10921, 10773},

  { ARM::BI__builtin_arm_mve_veorq_u16, 10930, 10773},

  { ARM::BI__builtin_arm_mve_veorq_u32, 10940, 10773},

  { ARM::BI__builtin_arm_mve_veorq_u8, 10950, 10773},

  { ARM::BI__builtin_arm_mve_veorq_x_f16, 10967, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_f32, 10979, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_s16, 10991, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_s32, 11003, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_s8, 11015, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_u16, 11026, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_u32, 11038, 10959},

  { ARM::BI__builtin_arm_mve_veorq_x_u8, 11050, 10959},

  { ARM::BI__builtin_arm_mve_vfmaq_f16, 11067, 11061},

  { ARM::BI__builtin_arm_mve_vfmaq_f32, 11077, 11061},

  { ARM::BI__builtin_arm_mve_vfmaq_m_f16, 11095, 11087},

  { ARM::BI__builtin_arm_mve_vfmaq_m_f32, 11107, 11087},

  { ARM::BI__builtin_arm_mve_vfmaq_m_n_f16, 11119, 11087},

  { ARM::BI__builtin_arm_mve_vfmaq_m_n_f32, 11133, 11087},

  { ARM::BI__builtin_arm_mve_vfmaq_n_f16, 11147, 11061},

  { ARM::BI__builtin_arm_mve_vfmaq_n_f32, 11159, 11061},

  { ARM::BI__builtin_arm_mve_vfmasq_m_n_f16, 11180, 11171},

  { ARM::BI__builtin_arm_mve_vfmasq_m_n_f32, 11195, 11171},

  { ARM::BI__builtin_arm_mve_vfmasq_n_f16, 11217, 11210},

  { ARM::BI__builtin_arm_mve_vfmasq_n_f32, 11230, 11210},

  { ARM::BI__builtin_arm_mve_vfmsq_f16, 11249, 11243},

  { ARM::BI__builtin_arm_mve_vfmsq_f32, 11259, 11243},

  { ARM::BI__builtin_arm_mve_vfmsq_m_f16, 11277, 11269},

  { ARM::BI__builtin_arm_mve_vfmsq_m_f32, 11289, 11269},

  { ARM::BI__builtin_arm_mve_vgetq_lane_f16, 11312, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_f32, 11327, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_s16, 11342, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_s32, 11357, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_s64, 11372, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_s8, 11387, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_u16, 11401, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_u32, 11416, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_u64, 11431, 11301},

  { ARM::BI__builtin_arm_mve_vgetq_lane_u8, 11446, 11301},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_s16, 11469, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_s32, 11484, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_s8, 11499, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_u16, 11513, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_u32, 11528, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_n_u8, 11543, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_s16, 11557, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_s32, 11570, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_s8, 11583, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_u16, 11595, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_u32, 11608, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_m_u8, 11621, 11460},

  { ARM::BI__builtin_arm_mve_vhaddq_n_s16, 11640, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_n_s32, 11653, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_n_s8, 11666, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_n_u16, 11678, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_n_u32, 11691, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_n_u8, 11704, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_s16, 11716, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_s32, 11727, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_s8, 11738, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_u16, 11748, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_u32, 11759, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_u8, 11770, 11633},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_s16, 11789, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_s32, 11804, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_s8, 11819, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_u16, 11833, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_u32, 11848, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_n_u8, 11863, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_s16, 11877, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_s32, 11890, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_s8, 11903, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_u16, 11915, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_u32, 11928, 11780},

  { ARM::BI__builtin_arm_mve_vhaddq_x_u8, 11941, 11780},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s16, 11970, 11953},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s32, 11991, 11953},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_m_s8, 12012, 11953},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s16, 12047, 12032},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s32, 12066, 12032},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_s8, 12085, 12032},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s16, 12120, 12103},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s32, 12141, 12103},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot270_x_s8, 12162, 12103},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s16, 12198, 12182},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s32, 12218, 12182},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_m_s8, 12238, 12182},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s16, 12271, 12257},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s32, 12289, 12257},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_s8, 12307, 12257},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s16, 12340, 12324},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s32, 12360, 12324},

  { ARM::BI__builtin_arm_mve_vhcaddq_rot90_x_s8, 12380, 12324},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_s16, 12408, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_s32, 12423, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_s8, 12438, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_u16, 12452, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_u32, 12467, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_n_u8, 12482, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_s16, 12496, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_s32, 12509, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_s8, 12522, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_u16, 12534, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_u32, 12547, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_m_u8, 12560, 12399},

  { ARM::BI__builtin_arm_mve_vhsubq_n_s16, 12579, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_n_s32, 12592, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_n_s8, 12605, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_n_u16, 12617, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_n_u32, 12630, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_n_u8, 12643, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_s16, 12655, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_s32, 12666, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_s8, 12677, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_u16, 12687, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_u32, 12698, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_u8, 12709, 12572},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_s16, 12728, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_s32, 12743, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_s8, 12758, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_u16, 12772, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_u32, 12787, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_n_u8, 12802, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_s16, 12816, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_s32, 12829, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_s8, 12842, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_u16, 12854, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_u32, 12867, 12719},

  { ARM::BI__builtin_arm_mve_vhsubq_x_u8, 12880, 12719},

  { ARM::BI__builtin_arm_mve_vidupq_m_n_u16, 12901, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_m_n_u32, 12916, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_m_n_u8, 12931, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_m_wb_u16, 12945, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_m_wb_u32, 12961, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_m_wb_u8, 12977, 12892},

  { ARM::BI__builtin_arm_mve_vidupq_n_u16, 13003, 12992},

  { ARM::BI__builtin_arm_mve_vidupq_n_u32, 13027, 13016},

  { ARM::BI__builtin_arm_mve_vidupq_n_u8, 13050, 13040},

  { ARM::BI__builtin_arm_mve_vidupq_wb_u16, 13062, 12992},

  { ARM::BI__builtin_arm_mve_vidupq_wb_u32, 13076, 13016},

  { ARM::BI__builtin_arm_mve_vidupq_wb_u8, 13090, 13040},

  { ARM::BI__builtin_arm_mve_vidupq_x_n_u16, 13116, 13103},

  { ARM::BI__builtin_arm_mve_vidupq_x_n_u32, 13144, 13131},

  { ARM::BI__builtin_arm_mve_vidupq_x_n_u8, 13171, 13159},

  { ARM::BI__builtin_arm_mve_vidupq_x_wb_u16, 13185, 13103},

  { ARM::BI__builtin_arm_mve_vidupq_x_wb_u32, 13201, 13131},

  { ARM::BI__builtin_arm_mve_vidupq_x_wb_u8, 13217, 13159},

  { ARM::BI__builtin_arm_mve_viwdupq_m_n_u16, 13242, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_m_n_u32, 13258, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_m_n_u8, 13274, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u16, 13289, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u32, 13306, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_m_wb_u8, 13323, 13232},

  { ARM::BI__builtin_arm_mve_viwdupq_n_u16, 13351, 13339},

  { ARM::BI__builtin_arm_mve_viwdupq_n_u32, 13377, 13365},

  { ARM::BI__builtin_arm_mve_viwdupq_n_u8, 13402, 13391},

  { ARM::BI__builtin_arm_mve_viwdupq_wb_u16, 13415, 13339},

  { ARM::BI__builtin_arm_mve_viwdupq_wb_u32, 13430, 13365},

  { ARM::BI__builtin_arm_mve_viwdupq_wb_u8, 13445, 13391},

  { ARM::BI__builtin_arm_mve_viwdupq_x_n_u16, 13473, 13459},

  { ARM::BI__builtin_arm_mve_viwdupq_x_n_u32, 13503, 13489},

  { ARM::BI__builtin_arm_mve_viwdupq_x_n_u8, 13532, 13519},

  { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u16, 13547, 13459},

  { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u32, 13564, 13489},

  { ARM::BI__builtin_arm_mve_viwdupq_x_wb_u8, 13581, 13519},

  { ARM::BI__builtin_arm_mve_vld1q_f16, 13603, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_f32, 13613, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_s16, 13623, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_s32, 13633, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_s8, 13643, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_u16, 13652, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_u32, 13662, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_u8, 13672, 13597},

  { ARM::BI__builtin_arm_mve_vld1q_z_f16, 13689, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_f32, 13701, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_s16, 13713, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_s32, 13725, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_s8, 13737, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_u16, 13748, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_u32, 13760, 13681},

  { ARM::BI__builtin_arm_mve_vld1q_z_u8, 13772, 13681},

  { ARM::BI__builtin_arm_mve_vld2q_f16, 13789, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_f32, 13799, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_s16, 13809, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_s32, 13819, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_s8, 13829, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_u16, 13838, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_u32, 13848, 13783},

  { ARM::BI__builtin_arm_mve_vld2q_u8, 13858, 13783},

  { ARM::BI__builtin_arm_mve_vld4q_f16, 13873, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_f32, 13883, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_s16, 13893, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_s32, 13903, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_s8, 13913, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_u16, 13922, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_u32, 13932, 13867},

  { ARM::BI__builtin_arm_mve_vld4q_u8, 13942, 13867},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s16, 13972, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s32, 13997, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_s8, 14022, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u16, 14046, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u32, 14071, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_u8, 14096, 13951},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s16, 14143, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s32, 14170, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_s8, 14197, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u16, 14223, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u32, 14250, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_gather_offset_z_u8, 14277, 14120},

  { ARM::BI__builtin_arm_mve_vldrbq_s16, 14303, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_s32, 14314, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_s8, 14325, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_u16, 14335, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_u32, 14346, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_u8, 14357, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_s16, 14367, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_s32, 14380, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_s8, 14393, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_u16, 14405, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_u32, 14418, -1},

  { ARM::BI__builtin_arm_mve_vldrbq_z_u8, 14431, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_s64, 14443, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_u64, 14466, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_s64, 14489, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_u64, 14515, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_s64, 14541, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_wb_z_u64, 14569, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_s64, 14597, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_base_z_u64, 14622, -1},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_s64, 14668, 14647},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_u64, 14693, 14647},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_z_s64, 14741, 14718},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_offset_z_u64, 14768, 14718},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_s64, 14824, 14795},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_u64, 14857, 14795},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_z_s64, 14921, 14890},

  { ARM::BI__builtin_arm_mve_vldrdq_gather_shifted_offset_z_u64, 14956, 14890},

  { ARM::BI__builtin_arm_mve_vldrhq_f16, 14991, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_f16, 15023, 15002},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_s16, 15048, 15002},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_s32, 15073, 15002},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_u16, 15098, 15002},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_u32, 15123, 15002},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_f16, 15171, 15148},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_s16, 15198, 15148},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_s32, 15225, 15148},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_u16, 15252, 15148},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_offset_z_u32, 15279, 15148},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_f16, 15335, 15306},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_s16, 15368, 15306},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_s32, 15401, 15306},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_u16, 15434, 15306},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_u32, 15467, 15306},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_f16, 15531, 15500},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_s16, 15566, 15500},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_s32, 15601, 15500},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_u16, 15636, 15500},

  { ARM::BI__builtin_arm_mve_vldrhq_gather_shifted_offset_z_u32, 15671, 15500},

  { ARM::BI__builtin_arm_mve_vldrhq_s16, 15706, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_s32, 15717, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_u16, 15728, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_u32, 15739, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_z_f16, 15750, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_z_s16, 15763, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_z_s32, 15776, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_z_u16, 15789, -1},

  { ARM::BI__builtin_arm_mve_vldrhq_z_u32, 15802, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_f32, 15815, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_f32, 15826, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_s32, 15849, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_u32, 15872, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_f32, 15895, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_s32, 15921, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_u32, 15947, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_f32, 15973, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_s32, 16001, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_wb_z_u32, 16029, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_f32, 16057, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_s32, 16082, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_base_z_u32, 16107, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_f32, 16153, 16132},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_s32, 16178, 16132},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_u32, 16203, 16132},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_f32, 16251, 16228},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_s32, 16278, 16228},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_offset_z_u32, 16305, 16228},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_f32, 16361, 16332},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_s32, 16394, 16332},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_u32, 16427, 16332},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_f32, 16491, 16460},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_s32, 16526, 16460},

  { ARM::BI__builtin_arm_mve_vldrwq_gather_shifted_offset_z_u32, 16561, 16460},

  { ARM::BI__builtin_arm_mve_vldrwq_s32, 16596, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_u32, 16607, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_z_f32, 16618, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_z_s32, 16631, -1},

  { ARM::BI__builtin_arm_mve_vldrwq_z_u32, 16644, -1},

  { ARM::BI__builtin_arm_mve_vmaxaq_m_s16, 16666, 16657},

  { ARM::BI__builtin_arm_mve_vmaxaq_m_s32, 16679, 16657},

  { ARM::BI__builtin_arm_mve_vmaxaq_m_s8, 16692, 16657},

  { ARM::BI__builtin_arm_mve_vmaxaq_s16, 16711, 16704},

  { ARM::BI__builtin_arm_mve_vmaxaq_s32, 16722, 16704},

  { ARM::BI__builtin_arm_mve_vmaxaq_s8, 16733, 16704},

  { ARM::BI__builtin_arm_mve_vmaxavq_p_s16, 16753, 16743},

  { ARM::BI__builtin_arm_mve_vmaxavq_p_s32, 16767, 16743},

  { ARM::BI__builtin_arm_mve_vmaxavq_p_s8, 16781, 16743},

  { ARM::BI__builtin_arm_mve_vmaxavq_s16, 16802, 16794},

  { ARM::BI__builtin_arm_mve_vmaxavq_s32, 16814, 16794},

  { ARM::BI__builtin_arm_mve_vmaxavq_s8, 16826, 16794},

  { ARM::BI__builtin_arm_mve_vmaxnmaq_f16, 16846, 16837},

  { ARM::BI__builtin_arm_mve_vmaxnmaq_f32, 16859, 16837},

  { ARM::BI__builtin_arm_mve_vmaxnmaq_m_f16, 16883, 16872},

  { ARM::BI__builtin_arm_mve_vmaxnmaq_m_f32, 16898, 16872},

  { ARM::BI__builtin_arm_mve_vmaxnmavq_f16, 16923, 16913},

  { ARM::BI__builtin_arm_mve_vmaxnmavq_f32, 16937, 16913},

  { ARM::BI__builtin_arm_mve_vmaxnmavq_p_f16, 16963, 16951},

  { ARM::BI__builtin_arm_mve_vmaxnmavq_p_f32, 16979, 16951},

  { ARM::BI__builtin_arm_mve_vmaxnmq_f16, 17003, 16995},

  { ARM::BI__builtin_arm_mve_vmaxnmq_f32, 17015, 16995},

  { ARM::BI__builtin_arm_mve_vmaxnmq_m_f16, 17037, 17027},

  { ARM::BI__builtin_arm_mve_vmaxnmq_m_f32, 17051, 17027},

  { ARM::BI__builtin_arm_mve_vmaxnmq_x_f16, 17075, 17065},

  { ARM::BI__builtin_arm_mve_vmaxnmq_x_f32, 17089, 17065},

  { ARM::BI__builtin_arm_mve_vmaxnmvq_f16, 17112, 17103},

  { ARM::BI__builtin_arm_mve_vmaxnmvq_f32, 17125, 17103},

  { ARM::BI__builtin_arm_mve_vmaxnmvq_p_f16, 17149, 17138},

  { ARM::BI__builtin_arm_mve_vmaxnmvq_p_f32, 17164, 17138},

  { ARM::BI__builtin_arm_mve_vmaxq_m_s16, 17187, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_m_s32, 17199, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_m_s8, 17211, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_m_u16, 17222, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_m_u32, 17234, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_m_u8, 17246, 17179},

  { ARM::BI__builtin_arm_mve_vmaxq_s16, 17263, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_s32, 17273, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_s8, 17283, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_u16, 17292, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_u32, 17302, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_u8, 17312, 17257},

  { ARM::BI__builtin_arm_mve_vmaxq_x_s16, 17329, 17321},

  { ARM::BI__builtin_arm_mve_vmaxq_x_s32, 17341, 17321},

  { ARM::BI__builtin_arm_mve_vmaxq_x_s8, 17353, 17321},

  { ARM::BI__builtin_arm_mve_vmaxq_x_u16, 17364, 17321},

  { ARM::BI__builtin_arm_mve_vmaxq_x_u32, 17376, 17321},

  { ARM::BI__builtin_arm_mve_vmaxq_x_u8, 17388, 17321},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_s16, 17408, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_s32, 17421, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_s8, 17434, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_u16, 17446, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_u32, 17459, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_p_u8, 17472, 17399},

  { ARM::BI__builtin_arm_mve_vmaxvq_s16, 17491, 17484},

  { ARM::BI__builtin_arm_mve_vmaxvq_s32, 17502, 17484},

  { ARM::BI__builtin_arm_mve_vmaxvq_s8, 17513, 17484},

  { ARM::BI__builtin_arm_mve_vmaxvq_u16, 17523, 17484},

  { ARM::BI__builtin_arm_mve_vmaxvq_u32, 17534, 17484},

  { ARM::BI__builtin_arm_mve_vmaxvq_u8, 17545, 17484},

  { ARM::BI__builtin_arm_mve_vminaq_m_s16, 17564, 17555},

  { ARM::BI__builtin_arm_mve_vminaq_m_s32, 17577, 17555},

  { ARM::BI__builtin_arm_mve_vminaq_m_s8, 17590, 17555},

  { ARM::BI__builtin_arm_mve_vminaq_s16, 17609, 17602},

  { ARM::BI__builtin_arm_mve_vminaq_s32, 17620, 17602},

  { ARM::BI__builtin_arm_mve_vminaq_s8, 17631, 17602},

  { ARM::BI__builtin_arm_mve_vminavq_p_s16, 17651, 17641},

  { ARM::BI__builtin_arm_mve_vminavq_p_s32, 17665, 17641},

  { ARM::BI__builtin_arm_mve_vminavq_p_s8, 17679, 17641},

  { ARM::BI__builtin_arm_mve_vminavq_s16, 17700, 17692},

  { ARM::BI__builtin_arm_mve_vminavq_s32, 17712, 17692},

  { ARM::BI__builtin_arm_mve_vminavq_s8, 17724, 17692},

  { ARM::BI__builtin_arm_mve_vminnmaq_f16, 17744, 17735},

  { ARM::BI__builtin_arm_mve_vminnmaq_f32, 17757, 17735},

  { ARM::BI__builtin_arm_mve_vminnmaq_m_f16, 17781, 17770},

  { ARM::BI__builtin_arm_mve_vminnmaq_m_f32, 17796, 17770},

  { ARM::BI__builtin_arm_mve_vminnmavq_f16, 17821, 17811},

  { ARM::BI__builtin_arm_mve_vminnmavq_f32, 17835, 17811},

  { ARM::BI__builtin_arm_mve_vminnmavq_p_f16, 17861, 17849},

  { ARM::BI__builtin_arm_mve_vminnmavq_p_f32, 17877, 17849},

  { ARM::BI__builtin_arm_mve_vminnmq_f16, 17901, 17893},

  { ARM::BI__builtin_arm_mve_vminnmq_f32, 17913, 17893},

  { ARM::BI__builtin_arm_mve_vminnmq_m_f16, 17935, 17925},

  { ARM::BI__builtin_arm_mve_vminnmq_m_f32, 17949, 17925},

  { ARM::BI__builtin_arm_mve_vminnmq_x_f16, 17973, 17963},

  { ARM::BI__builtin_arm_mve_vminnmq_x_f32, 17987, 17963},

  { ARM::BI__builtin_arm_mve_vminnmvq_f16, 18010, 18001},

  { ARM::BI__builtin_arm_mve_vminnmvq_f32, 18023, 18001},

  { ARM::BI__builtin_arm_mve_vminnmvq_p_f16, 18047, 18036},

  { ARM::BI__builtin_arm_mve_vminnmvq_p_f32, 18062, 18036},

  { ARM::BI__builtin_arm_mve_vminq_m_s16, 18085, 18077},

  { ARM::BI__builtin_arm_mve_vminq_m_s32, 18097, 18077},

  { ARM::BI__builtin_arm_mve_vminq_m_s8, 18109, 18077},

  { ARM::BI__builtin_arm_mve_vminq_m_u16, 18120, 18077},

  { ARM::BI__builtin_arm_mve_vminq_m_u32, 18132, 18077},

  { ARM::BI__builtin_arm_mve_vminq_m_u8, 18144, 18077},

  { ARM::BI__builtin_arm_mve_vminq_s16, 18161, 18155},

  { ARM::BI__builtin_arm_mve_vminq_s32, 18171, 18155},

  { ARM::BI__builtin_arm_mve_vminq_s8, 18181, 18155},

  { ARM::BI__builtin_arm_mve_vminq_u16, 18190, 18155},

  { ARM::BI__builtin_arm_mve_vminq_u32, 18200, 18155},

  { ARM::BI__builtin_arm_mve_vminq_u8, 18210, 18155},

  { ARM::BI__builtin_arm_mve_vminq_x_s16, 18227, 18219},

  { ARM::BI__builtin_arm_mve_vminq_x_s32, 18239, 18219},

  { ARM::BI__builtin_arm_mve_vminq_x_s8, 18251, 18219},

  { ARM::BI__builtin_arm_mve_vminq_x_u16, 18262, 18219},

  { ARM::BI__builtin_arm_mve_vminq_x_u32, 18274, 18219},

  { ARM::BI__builtin_arm_mve_vminq_x_u8, 18286, 18219},

  { ARM::BI__builtin_arm_mve_vminvq_p_s16, 18306, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_p_s32, 18319, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_p_s8, 18332, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_p_u16, 18344, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_p_u32, 18357, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_p_u8, 18370, 18297},

  { ARM::BI__builtin_arm_mve_vminvq_s16, 18389, 18382},

  { ARM::BI__builtin_arm_mve_vminvq_s32, 18400, 18382},

  { ARM::BI__builtin_arm_mve_vminvq_s8, 18411, 18382},

  { ARM::BI__builtin_arm_mve_vminvq_u16, 18421, 18382},

  { ARM::BI__builtin_arm_mve_vminvq_u32, 18432, 18382},

  { ARM::BI__builtin_arm_mve_vminvq_u8, 18443, 18382},