Subversion Repositories QNX 8.QNX8 LLVM/Clang compiler suite

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Rev Author Line No. Line
14 pmbaty 1 
case ARM::BI__builtin_arm_cde_cx1:
2 
case ARM::BI__builtin_arm_cde_cx1d:
3 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
4 
         SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x1FFF);
5 
  break;
6 
case ARM::BI__builtin_arm_cde_vcx1_u32:
7 
case ARM::BI__builtin_arm_cde_vcx1d_u64:
8 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
9 
         SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0x7FF);
10 
  break;
11 
case ARM::BI__builtin_arm_cde_vcx1q_u8:
12 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
13 
         SemaBuiltinConstantArgRange(TheCall, 1, 0x0, 0xFFF);
14 
  break;
15 
case ARM::BI__builtin_arm_cde_cx2:
16 
case ARM::BI__builtin_arm_cde_cx2d:
17 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
18 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x1FF);
19 
  break;
20 
case ARM::BI__builtin_arm_cde_cx1a:
21 
case ARM::BI__builtin_arm_cde_cx1da:
22 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
23 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x1FFF);
24 
  break;
25 
case ARM::BI__builtin_arm_cde_vcx2_u32:
26 
case ARM::BI__builtin_arm_cde_vcx2d_u64:
27 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
28 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x3F);
29 
  break;
30 
case ARM::BI__builtin_arm_cde_vcx2q_f16:
31 
case ARM::BI__builtin_arm_cde_vcx2q_f32:
32 
case ARM::BI__builtin_arm_cde_vcx2q_s16:
33 
case ARM::BI__builtin_arm_cde_vcx2q_s32:
34 
case ARM::BI__builtin_arm_cde_vcx2q_s64:
35 
case ARM::BI__builtin_arm_cde_vcx2q_s8:
36 
case ARM::BI__builtin_arm_cde_vcx2q_u16:
37 
case ARM::BI__builtin_arm_cde_vcx2q_u32:
38 
case ARM::BI__builtin_arm_cde_vcx2q_u64:
39 
case ARM::BI__builtin_arm_cde_vcx2q_u8:
40 
case ARM::BI__builtin_arm_cde_vcx2q_u8_f16:
41 
case ARM::BI__builtin_arm_cde_vcx2q_u8_f32:
42 
case ARM::BI__builtin_arm_cde_vcx2q_u8_s16:
43 
case ARM::BI__builtin_arm_cde_vcx2q_u8_s32:
44 
case ARM::BI__builtin_arm_cde_vcx2q_u8_s64:
45 
case ARM::BI__builtin_arm_cde_vcx2q_u8_s8:
46 
case ARM::BI__builtin_arm_cde_vcx2q_u8_u16:
47 
case ARM::BI__builtin_arm_cde_vcx2q_u8_u32:
48 
case ARM::BI__builtin_arm_cde_vcx2q_u8_u64:
49 
case ARM::BI__builtin_arm_cde_vcx2q_u8_u8:
50 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
51 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x7F);
52 
  break;
53 
case ARM::BI__builtin_arm_cde_vcx1a_u32:
54 
case ARM::BI__builtin_arm_cde_vcx1da_u64:
55 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
56 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0x7FF);
57 
  break;
58 
case ARM::BI__builtin_arm_cde_vcx1q_m_f16:
59 
case ARM::BI__builtin_arm_cde_vcx1q_m_f32:
60 
case ARM::BI__builtin_arm_cde_vcx1q_m_s16:
61 
case ARM::BI__builtin_arm_cde_vcx1q_m_s32:
62 
case ARM::BI__builtin_arm_cde_vcx1q_m_s64:
63 
case ARM::BI__builtin_arm_cde_vcx1q_m_s8:
64 
case ARM::BI__builtin_arm_cde_vcx1q_m_u16:
65 
case ARM::BI__builtin_arm_cde_vcx1q_m_u32:
66 
case ARM::BI__builtin_arm_cde_vcx1q_m_u64:
67 
case ARM::BI__builtin_arm_cde_vcx1q_m_u8:
68 
case ARM::BI__builtin_arm_cde_vcx1qa_f16:
69 
case ARM::BI__builtin_arm_cde_vcx1qa_f32:
70 
case ARM::BI__builtin_arm_cde_vcx1qa_m_f16:
71 
case ARM::BI__builtin_arm_cde_vcx1qa_m_f32:
72 
case ARM::BI__builtin_arm_cde_vcx1qa_m_s16:
73 
case ARM::BI__builtin_arm_cde_vcx1qa_m_s32:
74 
case ARM::BI__builtin_arm_cde_vcx1qa_m_s64:
75 
case ARM::BI__builtin_arm_cde_vcx1qa_m_s8:
76 
case ARM::BI__builtin_arm_cde_vcx1qa_m_u16:
77 
case ARM::BI__builtin_arm_cde_vcx1qa_m_u32:
78 
case ARM::BI__builtin_arm_cde_vcx1qa_m_u64:
79 
case ARM::BI__builtin_arm_cde_vcx1qa_m_u8:
80 
case ARM::BI__builtin_arm_cde_vcx1qa_s16:
81 
case ARM::BI__builtin_arm_cde_vcx1qa_s32:
82 
case ARM::BI__builtin_arm_cde_vcx1qa_s64:
83 
case ARM::BI__builtin_arm_cde_vcx1qa_s8:
84 
case ARM::BI__builtin_arm_cde_vcx1qa_u16:
85 
case ARM::BI__builtin_arm_cde_vcx1qa_u32:
86 
case ARM::BI__builtin_arm_cde_vcx1qa_u64:
87 
case ARM::BI__builtin_arm_cde_vcx1qa_u8:
88 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
89 
         SemaBuiltinConstantArgRange(TheCall, 2, 0x0, 0xFFF);
90 
  break;
91 
case ARM::BI__builtin_arm_cde_cx2a:
92 
case ARM::BI__builtin_arm_cde_cx2da:
93 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
94 
         SemaBuiltinConstantArgRange(TheCall, 3, 0x0, 0x1FF);
95 
  break;
96 
case ARM::BI__builtin_arm_cde_cx3:
97 
case ARM::BI__builtin_arm_cde_cx3d:
98 
case ARM::BI__builtin_arm_cde_vcx2a_u32:
99 
case ARM::BI__builtin_arm_cde_vcx2da_u64:
100 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
101 
         SemaBuiltinConstantArgRange(TheCall, 3, 0x0, 0x3F);
102 
  break;
103 
case ARM::BI__builtin_arm_cde_vcx3_u32:
104 
case ARM::BI__builtin_arm_cde_vcx3d_u64:
105 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
106 
         SemaBuiltinConstantArgRange(TheCall, 3, 0x0, 0x7);
107 
  break;
108 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_f16:
109 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_f32:
110 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_s16:
111 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_s32:
112 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_s64:
113 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_s8:
114 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_u16:
115 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_u32:
116 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_u64:
117 
case ARM::BI__builtin_arm_cde_vcx2q_m_impl_u8:
118 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_f16:
119 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_f32:
120 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_s16:
121 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_s32:
122 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_s64:
123 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_s8:
124 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_u16:
125 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_u32:
126 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_u64:
127 
case ARM::BI__builtin_arm_cde_vcx2qa_impl_u8:
128 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_f16:
129 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_f32:
130 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s16:
131 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s32:
132 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s64:
133 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_s8:
134 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u16:
135 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u32:
136 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u64:
137 
case ARM::BI__builtin_arm_cde_vcx2qa_m_impl_u8:
138 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
139 
         SemaBuiltinConstantArgRange(TheCall, 3, 0x0, 0x7F);
140 
  break;
141 
case ARM::BI__builtin_arm_cde_vcx3q_impl_f16:
142 
case ARM::BI__builtin_arm_cde_vcx3q_impl_f32:
143 
case ARM::BI__builtin_arm_cde_vcx3q_impl_s16:
144 
case ARM::BI__builtin_arm_cde_vcx3q_impl_s32:
145 
case ARM::BI__builtin_arm_cde_vcx3q_impl_s64:
146 
case ARM::BI__builtin_arm_cde_vcx3q_impl_s8:
147 
case ARM::BI__builtin_arm_cde_vcx3q_impl_u16:
148 
case ARM::BI__builtin_arm_cde_vcx3q_impl_u32:
149 
case ARM::BI__builtin_arm_cde_vcx3q_impl_u64:
150 
case ARM::BI__builtin_arm_cde_vcx3q_impl_u8:
151 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_f16:
152 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_f32:
153 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s16:
154 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s32:
155 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s64:
156 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_s8:
157 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u16:
158 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u32:
159 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u64:
160 
case ARM::BI__builtin_arm_cde_vcx3q_u8_impl_u8:
161 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
162 
         SemaBuiltinConstantArgRange(TheCall, 3, 0x0, 0xF);
163 
  break;
164 
case ARM::BI__builtin_arm_cde_cx3a:
165 
case ARM::BI__builtin_arm_cde_cx3da:
166 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
167 
         SemaBuiltinConstantArgRange(TheCall, 4, 0x0, 0x3F);
168 
  break;
169 
case ARM::BI__builtin_arm_cde_vcx3a_u32:
170 
case ARM::BI__builtin_arm_cde_vcx3da_u64:
171 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
172 
         SemaBuiltinConstantArgRange(TheCall, 4, 0x0, 0x7);
173 
  break;
174 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_f16:
175 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_f32:
176 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_s16:
177 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_s32:
178 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_s64:
179 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_s8:
180 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_u16:
181 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_u32:
182 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_u64:
183 
case ARM::BI__builtin_arm_cde_vcx3q_m_impl_u8:
184 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_f16:
185 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_f32:
186 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_s16:
187 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_s32:
188 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_s64:
189 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_s8:
190 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_u16:
191 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_u32:
192 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_u64:
193 
case ARM::BI__builtin_arm_cde_vcx3qa_impl_u8:
194 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_f16:
195 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_f32:
196 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s16:
197 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s32:
198 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s64:
199 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_s8:
200 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u16:
201 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u32:
202 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u64:
203 
case ARM::BI__builtin_arm_cde_vcx3qa_m_impl_u8:
204 
  Err = SemaBuiltinConstantArgRange(TheCall, 0, 0x0, 0x7) ||
205 
         SemaBuiltinConstantArgRange(TheCall, 4, 0x0, 0xF);
206 
  break;