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14 | pmbaty | 1 | //===-- BuiltinsHexagon.def - Hexagon Builtin function database --*- C++ -*-==// |
2 | // |
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3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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4 | // See https://llvm.org/LICENSE.txt for license information. |
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5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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6 | // |
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7 | //===----------------------------------------------------------------------===// |
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8 | // |
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9 | // This file defines the Hexagon-specific builtin function database. Users of |
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10 | // this file must define the BUILTIN macro to make use of this information. |
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11 | // |
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12 | //===----------------------------------------------------------------------===// |
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13 | |||
14 | // The format of this database matches clang/Basic/Builtins.def. |
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15 | |||
16 | #if defined(BUILTIN) && !defined(TARGET_BUILTIN) |
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17 | # define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) |
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18 | #endif |
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19 | |||
20 | #pragma push_macro("V73") |
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21 | #define V73 "v73" |
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22 | #pragma push_macro("V71") |
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23 | #define V71 "v71|" V73 |
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24 | #pragma push_macro("V69") |
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25 | #define V69 "v69|" V71 |
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26 | #pragma push_macro("V68") |
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27 | #define V68 "v68|" V69 |
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28 | #pragma push_macro("V67") |
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29 | #define V67 "v67|" V68 |
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30 | #pragma push_macro("V66") |
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31 | #define V66 "v66|" V67 |
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32 | #pragma push_macro("V65") |
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33 | #define V65 "v65|" V66 |
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34 | #pragma push_macro("V62") |
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35 | #define V62 "v62|" V65 |
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36 | #pragma push_macro("V60") |
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37 | #define V60 "v60|" V62 |
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38 | #pragma push_macro("V55") |
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39 | #define V55 "v55|" V60 |
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40 | #pragma push_macro("V5") |
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41 | #define V5 "v5|" V55 |
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42 | |||
43 | #pragma push_macro("HVXV73") |
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44 | #define HVXV73 "hvxv73" |
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45 | #pragma push_macro("HVXV71") |
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46 | #define HVXV71 "hvxv71|" HVXV73 |
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47 | #pragma push_macro("HVXV69") |
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48 | #define HVXV69 "hvxv69|" HVXV71 |
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49 | #pragma push_macro("HVXV68") |
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50 | #define HVXV68 "hvxv68|" HVXV69 |
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51 | #pragma push_macro("HVXV67") |
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52 | #define HVXV67 "hvxv67|" HVXV68 |
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53 | #pragma push_macro("HVXV66") |
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54 | #define HVXV66 "hvxv66|" HVXV67 |
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55 | #pragma push_macro("HVXV65") |
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56 | #define HVXV65 "hvxv65|" HVXV66 |
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57 | #pragma push_macro("HVXV62") |
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58 | #define HVXV62 "hvxv62|" HVXV65 |
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59 | #pragma push_macro("HVXV60") |
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60 | #define HVXV60 "hvxv60|" HVXV62 |
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61 | |||
62 | |||
63 | // The builtins below are not autogenerated from iset.py. |
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64 | // Make sure you do not overwrite these. |
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65 | TARGET_BUILTIN(__builtin_SI_to_SXTHI_asrh, "ii", "", V5) |
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66 | TARGET_BUILTIN(__builtin_brev_ldd, "v*LLi*CLLi*iC", "", V5) |
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67 | TARGET_BUILTIN(__builtin_brev_ldw, "v*i*Ci*iC", "", V5) |
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68 | TARGET_BUILTIN(__builtin_brev_ldh, "v*s*Cs*iC", "", V5) |
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69 | TARGET_BUILTIN(__builtin_brev_lduh, "v*Us*CUs*iC", "", V5) |
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70 | TARGET_BUILTIN(__builtin_brev_ldb, "v*Sc*CSc*iC", "", V5) |
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71 | TARGET_BUILTIN(__builtin_brev_ldub, "v*Uc*CUc*iC", "", V5) |
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72 | TARGET_BUILTIN(__builtin_circ_ldd, "LLi*LLi*LLi*iIi", "", V5) |
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73 | TARGET_BUILTIN(__builtin_circ_ldw, "i*i*i*iIi", "", V5) |
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74 | TARGET_BUILTIN(__builtin_circ_ldh, "s*s*s*iIi", "", V5) |
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75 | TARGET_BUILTIN(__builtin_circ_lduh, "Us*Us*Us*iIi", "", V5) |
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76 | TARGET_BUILTIN(__builtin_circ_ldb, "c*c*c*iIi", "", V5) |
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77 | TARGET_BUILTIN(__builtin_circ_ldub, "Uc*Uc*Uc*iIi", "", V5) |
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78 | TARGET_BUILTIN(__builtin_brev_std, "LLi*CLLi*LLiiC", "", V5) |
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79 | TARGET_BUILTIN(__builtin_brev_stw, "i*Ci*iiC", "", V5) |
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80 | TARGET_BUILTIN(__builtin_brev_sth, "s*Cs*iiC", "", V5) |
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81 | TARGET_BUILTIN(__builtin_brev_sthhi, "s*Cs*iiC", "", V5) |
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82 | TARGET_BUILTIN(__builtin_brev_stb, "c*Cc*iiC", "", V5) |
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83 | TARGET_BUILTIN(__builtin_circ_std, "LLi*LLi*LLiiIi", "", V5) |
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84 | TARGET_BUILTIN(__builtin_circ_stw, "i*i*iiIi", "", V5) |
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85 | TARGET_BUILTIN(__builtin_circ_sth, "s*s*iiIi", "", V5) |
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86 | TARGET_BUILTIN(__builtin_circ_sthhi, "s*s*iiIi", "", V5) |
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87 | TARGET_BUILTIN(__builtin_circ_stb, "c*c*iiIi", "", V5) |
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88 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pci, "iv*IiivC*", "", V5) |
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89 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pci, "iv*IiivC*", "", V5) |
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90 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pci, "iv*IiivC*", "", V5) |
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91 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pci, "iv*IiivC*", "", V5) |
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92 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pci, "iv*IiivC*", "", V5) |
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93 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pci, "LLiv*IiivC*", "", V5) |
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94 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pcr, "iv*ivC*", "", V5) |
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95 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pcr, "iv*ivC*", "", V5) |
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96 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pcr, "iv*ivC*", "", V5) |
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97 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pcr, "iv*ivC*", "", V5) |
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98 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pcr, "iv*ivC*", "", V5) |
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99 | TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pcr, "LLiv*ivC*", "", V5) |
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100 | |||
101 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pci, "vv*IiiivC*", "", V5) |
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102 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pci, "vv*IiiivC*", "", V5) |
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103 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pci, "vv*IiiivC*", "", V5) |
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104 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pci, "vv*IiiivC*", "", V5) |
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105 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pci, "vv*IiiLLivC*", "", V5) |
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106 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pcr, "vv*iivC*", "", V5) |
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107 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pcr, "vv*iivC*", "", V5) |
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108 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pcr, "vv*iivC*", "", V5) |
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109 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pcr, "vv*iivC*", "", V5) |
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110 | TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pcr, "vv*iLLivC*", "", V5) |
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111 | |||
112 | TARGET_BUILTIN(__builtin_HEXAGON_prefetch,"vv*","", V5) |
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113 | TARGET_BUILTIN(__builtin_HEXAGON_A6_vminub_RdP,"LLiLLiLLi","", V62) |
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114 | |||
115 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq,"vV64bv*V16i","", HVXV60) |
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116 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq,"vV64bv*V16i","", HVXV60) |
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117 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq,"vV64bv*V16i","", HVXV60) |
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118 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq,"vV64bv*V16i","", HVXV60) |
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119 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq_128B,"vV128bv*V32i","", HVXV60) |
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120 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq_128B,"vV128bv*V32i","", HVXV60) |
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121 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq_128B,"vV128bv*V32i","", HVXV60) |
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122 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq_128B,"vV128bv*V32i","", HVXV60) |
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123 | |||
124 | |||
125 | // These are only valid on v65 |
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126 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt,"V32iV16iLLi","", "hvxv65") |
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127 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_128B,"V64iV32iLLi","", "hvxv65") |
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128 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65") |
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129 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65") |
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130 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt,"V32iV16iLLi","", "hvxv65") |
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131 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_128B,"V64iV32iLLi","", "hvxv65") |
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132 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65") |
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133 | TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65") |
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134 | |||
135 | #include "clang/Basic/BuiltinsHexagonDep.def" |
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136 | |||
137 | #pragma pop_macro("HVXV60") |
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138 | #pragma pop_macro("HVXV62") |
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139 | #pragma pop_macro("HVXV65") |
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140 | #pragma pop_macro("HVXV66") |
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141 | #pragma pop_macro("HVXV67") |
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142 | #pragma pop_macro("HVXV68") |
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143 | #pragma pop_macro("HVXV69") |
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144 | #pragma pop_macro("HVXV71") |
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145 | #pragma pop_macro("HVXV73") |
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146 | |||
147 | #pragma pop_macro("V5") |
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148 | #pragma pop_macro("V55") |
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149 | #pragma pop_macro("V60") |
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150 | #pragma pop_macro("V62") |
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151 | #pragma pop_macro("V65") |
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152 | #pragma pop_macro("V66") |
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153 | #pragma pop_macro("V67") |
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154 | #pragma pop_macro("V68") |
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155 | #pragma pop_macro("V69") |
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156 | #pragma pop_macro("V71") |
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157 | #pragma pop_macro("V73") |
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158 | |||
159 | #undef BUILTIN |
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160 | #undef TARGET_BUILTIN |
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161 |