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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | //===----------------------------------------------------------------------===// |
| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | |||
| 9 | #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ |
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| 10 | #define _HEXAGON_CIRC_BREV_INTRINSICS_H_ 1 |
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| 11 | |||
| 12 | #include <hexagon_protos.h> |
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| 13 | #include <stdint.h> |
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| 14 | |||
| 15 | /* Circular Load */ |
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| 16 | /* ========================================================================== |
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| 17 | Assembly Syntax: Return=instruction() |
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| 18 | C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 19 | Instruction Type: InstructionType |
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| 20 | Execution Slots: SLOT0123 |
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| 21 | ========================================================================== */ |
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| 22 | #define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K) \ |
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| 23 | { ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } |
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| 24 | |||
| 25 | /* ========================================================================== |
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| 26 | Assembly Syntax: Return=instruction() |
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| 27 | C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 28 | Instruction Type: InstructionType |
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| 29 | Execution Slots: SLOT0123 |
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| 30 | ========================================================================== */ |
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| 31 | #define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K) \ |
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| 32 | { ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } |
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| 33 | |||
| 34 | /* ========================================================================== |
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| 35 | Assembly Syntax: Return=instruction() |
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| 36 | C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 37 | Instruction Type: InstructionType |
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| 38 | Execution Slots: SLOT0123 |
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| 39 | ========================================================================== */ |
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| 40 | #define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K) \ |
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| 41 | { ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
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| 42 | |||
| 43 | /* ========================================================================== |
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| 44 | Assembly Syntax: Return=instruction() |
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| 45 | C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst, UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 46 | Instruction Type: InstructionType |
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| 47 | Execution Slots: SLOT0123 |
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| 48 | ========================================================================== */ |
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| 49 | #define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \ |
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| 50 | { ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
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| 51 | |||
| 52 | /* ========================================================================== |
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| 53 | Assembly Syntax: Return=instruction() |
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| 54 | C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 55 | Instruction Type: InstructionType |
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| 56 | Execution Slots: SLOT0123 |
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| 57 | ========================================================================== */ |
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| 58 | #define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K) \ |
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| 59 | { ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } |
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| 60 | |||
| 61 | /* ========================================================================== |
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| 62 | Assembly Syntax: Return=instruction() |
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| 63 | C Intrinsic Prototype: void Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 64 | Instruction Type: InstructionType |
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| 65 | Execution Slots: SLOT0123 |
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| 66 | ========================================================================== */ |
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| 67 | #define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \ |
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| 68 | { ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } |
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| 69 | |||
| 70 | /* Circular Store */ |
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| 71 | /* ========================================================================== |
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| 72 | Assembly Syntax: Return=instruction() |
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| 73 | C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 74 | Instruction Type: InstructionType |
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| 75 | Execution Slots: SLOT0123 |
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| 76 | ========================================================================== */ |
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| 77 | #define Q6_circ_store_update_D(src,ptr,incr,bufsize,K) \ |
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| 78 | { ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } |
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| 79 | |||
| 80 | /* ========================================================================== |
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| 81 | Assembly Syntax: Return=instruction() |
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| 82 | C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 83 | Instruction Type: InstructionType |
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| 84 | Execution Slots: SLOT0123 |
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| 85 | ========================================================================== */ |
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| 86 | #define Q6_circ_store_update_W(src,ptr,incr,bufsize,K) \ |
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| 87 | { ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } |
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| 88 | |||
| 89 | /* ========================================================================== |
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| 90 | Assembly Syntax: Return=instruction() |
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| 91 | C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 92 | Instruction Type: InstructionType |
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| 93 | Execution Slots: SLOT0123 |
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| 94 | ========================================================================== */ |
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| 95 | #define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \ |
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| 96 | { ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
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| 97 | |||
| 98 | /* ========================================================================== |
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| 99 | Assembly Syntax: Return=instruction() |
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| 100 | C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
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| 101 | Instruction Type: InstructionType |
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| 102 | Execution Slots: SLOT0123 |
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| 103 | ========================================================================== */ |
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| 104 | #define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \ |
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| 105 | { ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
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| 106 | |||
| 107 | /* ========================================================================== |
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| 108 | Assembly Syntax: Return=instruction() |
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| 109 | C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize, UWord64 K) |
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| 110 | Instruction Type: InstructionType |
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| 111 | Execution Slots: SLOT0123 |
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| 112 | ========================================================================== */ |
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| 113 | #define Q6_circ_store_update_B(src,ptr,incr,bufsize,K) \ |
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| 114 | { ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); } |
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| 115 | |||
| 116 | |||
| 117 | /* Bit Reverse Load */ |
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| 118 | /* ========================================================================== |
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| 119 | Assembly Syntax: Return=instruction() |
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| 120 | C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4) |
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| 121 | Instruction Type: InstructionType |
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| 122 | Execution Slots: SLOT0123 |
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| 123 | ========================================================================== */ |
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| 124 | #define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \ |
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| 125 | { ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); } |
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| 126 | |||
| 127 | /* ========================================================================== |
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| 128 | Assembly Syntax: Return=instruction() |
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| 129 | C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4) |
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| 130 | Instruction Type: InstructionType |
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| 131 | Execution Slots: SLOT0123 |
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| 132 | ========================================================================== */ |
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| 133 | #define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \ |
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| 134 | { ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); } |
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| 135 | |||
| 136 | /* ========================================================================== |
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| 137 | Assembly Syntax: Return=instruction() |
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| 138 | C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4) |
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| 139 | Instruction Type: InstructionType |
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| 140 | Execution Slots: SLOT0123 |
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| 141 | ========================================================================== */ |
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| 142 | #define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \ |
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| 143 | { ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } |
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| 144 | |||
| 145 | /* ========================================================================== |
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| 146 | Assembly Syntax: Return=instruction() |
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| 147 | C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst, UWord16 *ptr, UWord32 Iu4) |
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| 148 | Instruction Type: InstructionType |
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| 149 | Execution Slots: SLOT0123 |
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| 150 | ========================================================================== */ |
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| 151 | #define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \ |
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| 152 | { ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } |
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| 153 | |||
| 154 | /* ========================================================================== |
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| 155 | Assembly Syntax: Return=instruction() |
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| 156 | C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4) |
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| 157 | Instruction Type: InstructionType |
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| 158 | Execution Slots: SLOT0123 |
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| 159 | ========================================================================== */ |
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| 160 | #define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \ |
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| 161 | { ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); } |
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| 162 | |||
| 163 | /* ========================================================================== |
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| 164 | Assembly Syntax: Return=instruction() |
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| 165 | C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4) |
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| 166 | Instruction Type: InstructionType |
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| 167 | Execution Slots: SLOT0123 |
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| 168 | ========================================================================== */ |
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| 169 | #define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \ |
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| 170 | { ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); } |
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| 171 | |||
| 172 | /* Bit Reverse Store */ |
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| 173 | |||
| 174 | /* ========================================================================== |
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| 175 | Assembly Syntax: Return=instruction() |
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| 176 | C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4) |
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| 177 | Instruction Type: InstructionType |
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| 178 | Execution Slots: SLOT0123 |
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| 179 | ========================================================================== */ |
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| 180 | #define Q6_bitrev_store_update_D(src,ptr,log2bufsize) \ |
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| 181 | { ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); } |
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| 182 | |||
| 183 | /* ========================================================================== |
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| 184 | Assembly Syntax: Return=instruction() |
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| 185 | C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4) |
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| 186 | Instruction Type: InstructionType |
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| 187 | Execution Slots: SLOT0123 |
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| 188 | ========================================================================== */ |
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| 189 | #define Q6_bitrev_store_update_W(src,ptr,log2bufsize) \ |
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| 190 | { ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); } |
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| 191 | |||
| 192 | /* ========================================================================== |
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| 193 | Assembly Syntax: Return=instruction() |
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| 194 | C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4) |
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| 195 | Instruction Type: InstructionType |
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| 196 | Execution Slots: SLOT0123 |
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| 197 | ========================================================================== */ |
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| 198 | #define Q6_bitrev_store_update_HL(src,ptr,log2bufsize) \ |
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| 199 | { ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); } |
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| 200 | |||
| 201 | /* ========================================================================== |
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| 202 | Assembly Syntax: Return=instruction() |
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| 203 | C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4) |
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| 204 | Instruction Type: InstructionType |
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| 205 | Execution Slots: SLOT0123 |
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| 206 | ========================================================================== */ |
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| 207 | #define Q6_bitrev_store_update_HH(src,ptr,log2bufsize) \ |
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| 208 | { ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); } |
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| 209 | |||
| 210 | /* ========================================================================== |
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| 211 | Assembly Syntax: Return=instruction() |
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| 212 | C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4) |
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| 213 | Instruction Type: InstructionType |
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| 214 | Execution Slots: SLOT0123 |
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| 215 | ========================================================================== */ |
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| 216 | #define Q6_bitrev_store_update_B(src,ptr,log2bufsize) \ |
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| 217 | { ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); } |
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| 218 | |||
| 219 | |||
| 220 | #define HEXAGON_circ_ldd __builtin_circ_ldd |
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| 221 | #define HEXAGON_circ_ldw __builtin_circ_ldw |
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| 222 | #define HEXAGON_circ_ldh __builtin_circ_ldh |
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| 223 | #define HEXAGON_circ_lduh __builtin_circ_lduh |
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| 224 | #define HEXAGON_circ_ldb __builtin_circ_ldb |
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| 225 | #define HEXAGON_circ_ldub __builtin_circ_ldub |
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| 226 | |||
| 227 | |||
| 228 | #define HEXAGON_circ_std __builtin_circ_std |
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| 229 | #define HEXAGON_circ_stw __builtin_circ_stw |
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| 230 | #define HEXAGON_circ_sth __builtin_circ_sth |
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| 231 | #define HEXAGON_circ_sthhi __builtin_circ_sthhi |
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| 232 | #define HEXAGON_circ_stb __builtin_circ_stb |
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| 233 | |||
| 234 | |||
| 235 | #define HEXAGON_brev_ldd __builtin_brev_ldd |
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| 236 | #define HEXAGON_brev_ldw __builtin_brev_ldw |
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| 237 | #define HEXAGON_brev_ldh __builtin_brev_ldh |
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| 238 | #define HEXAGON_brev_lduh __builtin_brev_lduh |
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| 239 | #define HEXAGON_brev_ldb __builtin_brev_ldb |
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| 240 | #define HEXAGON_brev_ldub __builtin_brev_ldub |
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| 241 | |||
| 242 | #define HEXAGON_brev_std __builtin_brev_std |
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| 243 | #define HEXAGON_brev_stw __builtin_brev_stw |
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| 244 | #define HEXAGON_brev_sth __builtin_brev_sth |
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| 245 | #define HEXAGON_brev_sthhi __builtin_brev_sthhi |
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| 246 | #define HEXAGON_brev_stb __builtin_brev_stb |
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| 247 | |||
| 248 | #ifdef __HVX__ |
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| 249 | /* ========================================================================== |
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| 250 | Assembly Syntax: if (Qt) vmem(Rt+#0) = Vs |
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| 251 | C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
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| 252 | Instruction Type: COPROC_VMEM |
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| 253 | Execution Slots: SLOT0 |
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| 254 | ========================================================================== */ |
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| 255 | |||
| 256 | #define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq) |
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| 257 | |||
| 258 | /* ========================================================================== |
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| 259 | Assembly Syntax: if (!Qt) vmem(Rt+#0) = Vs |
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| 260 | C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
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| 261 | Instruction Type: COPROC_VMEM |
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| 262 | Execution Slots: SLOT0 |
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| 263 | ========================================================================== */ |
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| 264 | |||
| 265 | #define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq) |
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| 266 | |||
| 267 | /* ========================================================================== |
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| 268 | Assembly Syntax: if (Qt) vmem(Rt+#0):nt = Vs |
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| 269 | C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
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| 270 | Instruction Type: COPROC_VMEM |
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| 271 | Execution Slots: SLOT0 |
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| 272 | ========================================================================== */ |
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| 273 | |||
| 274 | #define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq) |
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| 275 | |||
| 276 | /* ========================================================================== |
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| 277 | Assembly Syntax: if (!Qt) vmem(Rt+#0):nt = Vs |
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| 278 | C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
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| 279 | Instruction Type: COPROC_VMEM |
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| 280 | Execution Slots: SLOT0 |
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| 281 | ========================================================================== */ |
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| 282 | |||
| 283 | #define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq) |
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| 284 | |||
| 285 | #endif |
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| 286 | |||
| 287 | |||
| 288 | #endif /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */ |
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| 289 | |||
| 290 | #ifdef __NOT_DEFINED__ |
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| 291 | /*** comment block template ***/ |
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| 292 | /* ========================================================================== |
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| 293 | Assembly Syntax: Return=instruction() |
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| 294 | C Intrinsic Prototype: ReturnType Intrinsic(ParamType Rs, ParamType Rt) |
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| 295 | Instruction Type: InstructionType |
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| 296 | Execution Slots: SLOT0123 |
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| 297 | ========================================================================== */ |
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| 298 | #endif /*** __NOT_DEFINED__ ***/ |