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/*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
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 *
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 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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 * See https://llvm.org/LICENSE.txt for license information.
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 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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 *
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 *===-----------------------------------------------------------------------===
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 */
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#if !defined __IMMINTRIN_H
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#error "Never use <f16cintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __F16CINTRIN_H
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#define __F16CINTRIN_H
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/* Define the default attributes for the functions in this file. */
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#define __DEFAULT_FN_ATTRS128 \
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  __attribute__((__always_inline__, __nodebug__, __target__("f16c"), __min_vector_width__(128)))
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#define __DEFAULT_FN_ATTRS256 \
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  __attribute__((__always_inline__, __nodebug__, __target__("f16c"), __min_vector_width__(256)))
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/* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
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 * but that's because icc can emulate these without f16c using a library call.
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 * Since we don't do that let's leave these in f16cintrin.h.
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 */
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/// Converts a 16-bit half-precision float value into a 32-bit float
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///    value.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.
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///
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/// \param __a
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///    A 16-bit half-precision float value.
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/// \returns The converted 32-bit float value.
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static __inline float __DEFAULT_FN_ATTRS128
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_cvtsh_ss(unsigned short __a)
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{
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  __v8hi __v = {(short)__a, 0, 0, 0, 0, 0, 0, 0};
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  __v4sf __r = __builtin_ia32_vcvtph2ps(__v);
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  return __r[0];
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}
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/// Converts a 32-bit single-precision float value to a 16-bit
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///    half-precision float value.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \code
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/// unsigned short _cvtss_sh(float a, const int imm);
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/// \endcode
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///
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/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.
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///
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/// \param a
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///    A 32-bit single-precision float value to be converted to a 16-bit
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///    half-precision float value.
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/// \param imm
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///    An immediate value controlling rounding using bits [2:0]: \n
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///    000: Nearest \n
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///    001: Down \n
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///    010: Up \n
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///    011: Truncate \n
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///    1XX: Use MXCSR.RC for rounding
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/// \returns The converted 16-bit half-precision float value.
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#define _cvtss_sh(a, imm) __extension__ ({ \
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  (unsigned short)(((__v8hi)__builtin_ia32_vcvtps2ph((__v4sf){a, 0, 0, 0}, \
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                                                     (imm)))[0]); })
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/// Converts a 128-bit vector containing 32-bit float values into a
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///    128-bit vector containing 16-bit half-precision float values.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \code
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/// __m128i _mm_cvtps_ph(__m128 a, const int imm);
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/// \endcode
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///
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/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.
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///
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/// \param a
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///    A 128-bit vector containing 32-bit float values.
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/// \param imm
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///    An immediate value controlling rounding using bits [2:0]: \n
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///    000: Nearest \n
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///    001: Down \n
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///    010: Up \n
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///    011: Truncate \n
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///    1XX: Use MXCSR.RC for rounding
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/// \returns A 128-bit vector containing converted 16-bit half-precision float
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///    values. The lower 64 bits are used to store the converted 16-bit
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///    half-precision floating-point values.
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#define _mm_cvtps_ph(a, imm) \
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  ((__m128i)__builtin_ia32_vcvtps2ph((__v4sf)(__m128)(a), (imm)))
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/// Converts a 128-bit vector containing 16-bit half-precision float
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///    values into a 128-bit vector containing 32-bit float values.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.
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///
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/// \param __a
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///    A 128-bit vector containing 16-bit half-precision float values. The lower
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///    64 bits are used in the conversion.
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/// \returns A 128-bit vector of [4 x float] containing converted float values.
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static __inline __m128 __DEFAULT_FN_ATTRS128
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_mm_cvtph_ps(__m128i __a)
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{
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  return (__m128)__builtin_ia32_vcvtph2ps((__v8hi)__a);
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}
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/// Converts a 256-bit vector of [8 x float] into a 128-bit vector
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///    containing 16-bit half-precision float values.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \code
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/// __m128i _mm256_cvtps_ph(__m256 a, const int imm);
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/// \endcode
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///
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/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.
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///
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/// \param a
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///    A 256-bit vector containing 32-bit single-precision float values to be
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///    converted to 16-bit half-precision float values.
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/// \param imm
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///    An immediate value controlling rounding using bits [2:0]: \n
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///    000: Nearest \n
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///    001: Down \n
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///    010: Up \n
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///    011: Truncate \n
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///    1XX: Use MXCSR.RC for rounding
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/// \returns A 128-bit vector containing the converted 16-bit half-precision
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///    float values.
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#define _mm256_cvtps_ph(a, imm) \
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 ((__m128i)__builtin_ia32_vcvtps2ph256((__v8sf)(__m256)(a), (imm)))
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/// Converts a 128-bit vector containing 16-bit half-precision float
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///    values into a 256-bit vector of [8 x float].
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.
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///
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/// \param __a
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///    A 128-bit vector containing 16-bit half-precision float values to be
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///    converted to 32-bit single-precision float values.
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/// \returns A vector of [8 x float] containing the converted 32-bit
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///    single-precision float values.
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static __inline __m256 __DEFAULT_FN_ATTRS256
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_mm256_cvtph_ps(__m128i __a)
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{
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  return (__m256)__builtin_ia32_vcvtph2ps256((__v8hi)__a);
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}
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#undef __DEFAULT_FN_ATTRS128
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#undef __DEFAULT_FN_ATTRS256
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#endif /* __F16CINTRIN_H */