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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | /*===---- arm_acle.h - ARM Non-Neon intrinsics -----------------------------=== |
| 2 | * |
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| 3 | * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | * See https://llvm.org/LICENSE.txt for license information. |
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| 5 | * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | * |
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| 7 | *===-----------------------------------------------------------------------=== |
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| 8 | */ |
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| 9 | |||
| 10 | #ifndef __ARM_ACLE_H |
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| 11 | #define __ARM_ACLE_H |
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| 12 | |||
| 13 | #ifndef __ARM_ACLE |
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| 14 | #error "ACLE intrinsics support not enabled." |
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| 15 | #endif |
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| 16 | |||
| 17 | #include <stdint.h> |
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| 18 | |||
| 19 | #if defined(__cplusplus) |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |||
| 23 | /* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */ |
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| 24 | /* 8.3 Memory barriers */ |
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| 25 | #if !__has_builtin(__dmb) |
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| 26 | #define __dmb(i) __builtin_arm_dmb(i) |
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| 27 | #endif |
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| 28 | #if !__has_builtin(__dsb) |
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| 29 | #define __dsb(i) __builtin_arm_dsb(i) |
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| 30 | #endif |
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| 31 | #if !__has_builtin(__isb) |
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| 32 | #define __isb(i) __builtin_arm_isb(i) |
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| 33 | #endif |
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| 34 | |||
| 35 | /* 8.4 Hints */ |
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| 36 | |||
| 37 | #if !__has_builtin(__wfi) |
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| 38 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfi(void) { |
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| 39 | __builtin_arm_wfi(); |
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| 40 | } |
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| 41 | #endif |
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| 42 | |||
| 43 | #if !__has_builtin(__wfe) |
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| 44 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfe(void) { |
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| 45 | __builtin_arm_wfe(); |
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| 46 | } |
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| 47 | #endif |
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| 48 | |||
| 49 | #if !__has_builtin(__sev) |
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| 50 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sev(void) { |
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| 51 | __builtin_arm_sev(); |
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| 52 | } |
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| 53 | #endif |
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| 54 | |||
| 55 | #if !__has_builtin(__sevl) |
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| 56 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sevl(void) { |
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| 57 | __builtin_arm_sevl(); |
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| 58 | } |
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| 59 | #endif |
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| 60 | |||
| 61 | #if !__has_builtin(__yield) |
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| 62 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __yield(void) { |
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| 63 | __builtin_arm_yield(); |
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| 64 | } |
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| 65 | #endif |
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| 66 | |||
| 67 | #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE |
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| 68 | #define __dbg(t) __builtin_arm_dbg(t) |
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| 69 | #endif |
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| 70 | |||
| 71 | /* 8.5 Swap */ |
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| 72 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 73 | __swp(uint32_t __x, volatile uint32_t *__p) { |
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| 74 | uint32_t v; |
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| 75 | do |
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| 76 | v = __builtin_arm_ldrex(__p); |
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| 77 | while (__builtin_arm_strex(__x, __p)); |
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| 78 | return v; |
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| 79 | } |
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| 80 | |||
| 81 | /* 8.6 Memory prefetch intrinsics */ |
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| 82 | /* 8.6.1 Data prefetch */ |
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| 83 | #define __pld(addr) __pldx(0, 0, 0, addr) |
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| 84 | |||
| 85 | #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE |
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| 86 | #define __pldx(access_kind, cache_level, retention_policy, addr) \ |
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| 87 | __builtin_arm_prefetch(addr, access_kind, 1) |
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| 88 | #else |
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| 89 | #define __pldx(access_kind, cache_level, retention_policy, addr) \ |
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| 90 | __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1) |
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| 91 | #endif |
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| 92 | |||
| 93 | /* 8.6.2 Instruction prefetch */ |
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| 94 | #define __pli(addr) __plix(0, 0, addr) |
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| 95 | |||
| 96 | #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE |
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| 97 | #define __plix(cache_level, retention_policy, addr) \ |
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| 98 | __builtin_arm_prefetch(addr, 0, 0) |
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| 99 | #else |
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| 100 | #define __plix(cache_level, retention_policy, addr) \ |
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| 101 | __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0) |
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| 102 | #endif |
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| 103 | |||
| 104 | /* 8.7 NOP */ |
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| 105 | #if !defined(_MSC_VER) || !defined(__aarch64__) |
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| 106 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) __nop(void) { |
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| 107 | __builtin_arm_nop(); |
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| 108 | } |
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| 109 | #endif |
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| 110 | |||
| 111 | /* 9 DATA-PROCESSING INTRINSICS */ |
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| 112 | /* 9.2 Miscellaneous data-processing intrinsics */ |
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| 113 | /* ROR */ |
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| 114 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 115 | __ror(uint32_t __x, uint32_t __y) { |
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| 116 | __y %= 32; |
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| 117 | if (__y == 0) |
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| 118 | return __x; |
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| 119 | return (__x >> __y) | (__x << (32 - __y)); |
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| 120 | } |
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| 121 | |||
| 122 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__)) |
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| 123 | __rorll(uint64_t __x, uint32_t __y) { |
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| 124 | __y %= 64; |
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| 125 | if (__y == 0) |
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| 126 | return __x; |
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| 127 | return (__x >> __y) | (__x << (64 - __y)); |
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| 128 | } |
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| 129 | |||
| 130 | static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__)) |
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| 131 | __rorl(unsigned long __x, uint32_t __y) { |
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| 132 | #if __SIZEOF_LONG__ == 4 |
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| 133 | return __ror(__x, __y); |
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| 134 | #else |
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| 135 | return __rorll(__x, __y); |
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| 136 | #endif |
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| 137 | } |
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| 138 | |||
| 139 | |||
| 140 | /* CLZ */ |
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| 141 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 142 | __clz(uint32_t __t) { |
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| 143 | return (uint32_t)__builtin_clz(__t); |
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| 144 | } |
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| 145 | |||
| 146 | static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__)) |
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| 147 | __clzl(unsigned long __t) { |
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| 148 | return (unsigned long)__builtin_clzl(__t); |
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| 149 | } |
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| 150 | |||
| 151 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__)) |
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| 152 | __clzll(uint64_t __t) { |
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| 153 | return (uint64_t)__builtin_clzll(__t); |
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| 154 | } |
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| 155 | |||
| 156 | /* CLS */ |
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| 157 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 158 | __cls(uint32_t __t) { |
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| 159 | return __builtin_arm_cls(__t); |
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| 160 | } |
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| 161 | |||
| 162 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 163 | __clsl(unsigned long __t) { |
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| 164 | #if __SIZEOF_LONG__ == 4 |
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| 165 | return __builtin_arm_cls(__t); |
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| 166 | #else |
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| 167 | return __builtin_arm_cls64(__t); |
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| 168 | #endif |
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| 169 | } |
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| 170 | |||
| 171 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 172 | __clsll(uint64_t __t) { |
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| 173 | return __builtin_arm_cls64(__t); |
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| 174 | } |
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| 175 | |||
| 176 | /* REV */ |
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| 177 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 178 | __rev(uint32_t __t) { |
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| 179 | return __builtin_bswap32(__t); |
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| 180 | } |
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| 181 | |||
| 182 | static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__)) |
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| 183 | __revl(unsigned long __t) { |
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| 184 | #if __SIZEOF_LONG__ == 4 |
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| 185 | return __builtin_bswap32(__t); |
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| 186 | #else |
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| 187 | return __builtin_bswap64(__t); |
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| 188 | #endif |
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| 189 | } |
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| 190 | |||
| 191 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__)) |
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| 192 | __revll(uint64_t __t) { |
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| 193 | return __builtin_bswap64(__t); |
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| 194 | } |
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| 195 | |||
| 196 | /* REV16 */ |
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| 197 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 198 | __rev16(uint32_t __t) { |
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| 199 | return __ror(__rev(__t), 16); |
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| 200 | } |
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| 201 | |||
| 202 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__)) |
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| 203 | __rev16ll(uint64_t __t) { |
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| 204 | return (((uint64_t)__rev16(__t >> 32)) << 32) | (uint64_t)__rev16((uint32_t)__t); |
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| 205 | } |
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| 206 | |||
| 207 | static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__)) |
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| 208 | __rev16l(unsigned long __t) { |
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| 209 | #if __SIZEOF_LONG__ == 4 |
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| 210 | return __rev16(__t); |
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| 211 | #else |
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| 212 | return __rev16ll(__t); |
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| 213 | #endif |
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| 214 | } |
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| 215 | |||
| 216 | /* REVSH */ |
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| 217 | static __inline__ int16_t __attribute__((__always_inline__, __nodebug__)) |
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| 218 | __revsh(int16_t __t) { |
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| 219 | return (int16_t)__builtin_bswap16((uint16_t)__t); |
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| 220 | } |
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| 221 | |||
| 222 | /* RBIT */ |
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| 223 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
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| 224 | __rbit(uint32_t __t) { |
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| 225 | return __builtin_arm_rbit(__t); |
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| 226 | } |
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| 227 | |||
| 228 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__)) |
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| 229 | __rbitll(uint64_t __t) { |
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| 230 | #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE |
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| 231 | return (((uint64_t)__builtin_arm_rbit(__t)) << 32) | |
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| 232 | __builtin_arm_rbit(__t >> 32); |
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| 233 | #else |
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| 234 | return __builtin_arm_rbit64(__t); |
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| 235 | #endif |
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| 236 | } |
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| 237 | |||
| 238 | static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__)) |
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| 239 | __rbitl(unsigned long __t) { |
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| 240 | #if __SIZEOF_LONG__ == 4 |
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| 241 | return __rbit(__t); |
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| 242 | #else |
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| 243 | return __rbitll(__t); |
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| 244 | #endif |
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| 245 | } |
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| 246 | |||
| 247 | /* |
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| 248 | * 9.3 16-bit multiplications |
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| 249 | */ |
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| 250 | #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP |
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| 251 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 252 | __smulbb(int32_t __a, int32_t __b) { |
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| 253 | return __builtin_arm_smulbb(__a, __b); |
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| 254 | } |
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| 255 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 256 | __smulbt(int32_t __a, int32_t __b) { |
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| 257 | return __builtin_arm_smulbt(__a, __b); |
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| 258 | } |
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| 259 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 260 | __smultb(int32_t __a, int32_t __b) { |
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| 261 | return __builtin_arm_smultb(__a, __b); |
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| 262 | } |
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| 263 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 264 | __smultt(int32_t __a, int32_t __b) { |
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| 265 | return __builtin_arm_smultt(__a, __b); |
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| 266 | } |
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| 267 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 268 | __smulwb(int32_t __a, int32_t __b) { |
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| 269 | return __builtin_arm_smulwb(__a, __b); |
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| 270 | } |
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| 271 | static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) |
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| 272 | __smulwt(int32_t __a, int32_t __b) { |
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| 273 | return __builtin_arm_smulwt(__a, __b); |
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| 274 | } |
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| 275 | #endif |
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| 276 | |||
| 277 | /* |
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| 278 | * 9.4 Saturating intrinsics |
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| 279 | * |
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| 280 | * FIXME: Change guard to their corresponding __ARM_FEATURE flag when Q flag |
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| 281 | * intrinsics are implemented and the flag is enabled. |
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| 282 | */ |
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| 283 | /* 9.4.1 Width-specified saturation intrinsics */ |
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| 284 | #if defined(__ARM_FEATURE_SAT) && __ARM_FEATURE_SAT |
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| 285 | #define __ssat(x, y) __builtin_arm_ssat(x, y) |
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| 286 | #define __usat(x, y) __builtin_arm_usat(x, y) |
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| 287 | #endif |
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| 288 | |||
| 289 | /* 9.4.2 Saturating addition and subtraction intrinsics */ |
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| 290 | #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP |
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| 291 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 292 | __qadd(int32_t __t, int32_t __v) { |
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| 293 | return __builtin_arm_qadd(__t, __v); |
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| 294 | } |
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| 295 | |||
| 296 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 297 | __qsub(int32_t __t, int32_t __v) { |
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| 298 | return __builtin_arm_qsub(__t, __v); |
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| 299 | } |
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| 300 | |||
| 301 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 302 | __qdbl(int32_t __t) { |
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| 303 | return __builtin_arm_qadd(__t, __t); |
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| 304 | } |
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| 305 | #endif |
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| 306 | |||
| 307 | /* 9.4.3 Accumultating multiplications */ |
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| 308 | #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP |
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| 309 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 310 | __smlabb(int32_t __a, int32_t __b, int32_t __c) { |
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| 311 | return __builtin_arm_smlabb(__a, __b, __c); |
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| 312 | } |
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| 313 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 314 | __smlabt(int32_t __a, int32_t __b, int32_t __c) { |
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| 315 | return __builtin_arm_smlabt(__a, __b, __c); |
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| 316 | } |
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| 317 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 318 | __smlatb(int32_t __a, int32_t __b, int32_t __c) { |
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| 319 | return __builtin_arm_smlatb(__a, __b, __c); |
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| 320 | } |
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| 321 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 322 | __smlatt(int32_t __a, int32_t __b, int32_t __c) { |
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| 323 | return __builtin_arm_smlatt(__a, __b, __c); |
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| 324 | } |
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| 325 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 326 | __smlawb(int32_t __a, int32_t __b, int32_t __c) { |
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| 327 | return __builtin_arm_smlawb(__a, __b, __c); |
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| 328 | } |
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| 329 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
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| 330 | __smlawt(int32_t __a, int32_t __b, int32_t __c) { |
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| 331 | return __builtin_arm_smlawt(__a, __b, __c); |
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| 332 | } |
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| 333 | #endif |
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| 334 | |||
| 335 | |||
| 336 | /* 9.5.4 Parallel 16-bit saturation */ |
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| 337 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
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| 338 | #define __ssat16(x, y) __builtin_arm_ssat16(x, y) |
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| 339 | #define __usat16(x, y) __builtin_arm_usat16(x, y) |
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| 340 | #endif |
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| 341 | |||
| 342 | /* 9.5.5 Packing and unpacking */ |
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| 343 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
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| 344 | typedef int32_t int8x4_t; |
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| 345 | typedef int32_t int16x2_t; |
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| 346 | typedef uint32_t uint8x4_t; |
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| 347 | typedef uint32_t uint16x2_t; |
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| 348 | |||
| 349 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
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| 350 | __sxtab16(int16x2_t __a, int8x4_t __b) { |
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| 351 | return __builtin_arm_sxtab16(__a, __b); |
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| 352 | } |
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| 353 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
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| 354 | __sxtb16(int8x4_t __a) { |
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| 355 | return __builtin_arm_sxtb16(__a); |
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| 356 | } |
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| 357 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
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| 358 | __uxtab16(int16x2_t __a, int8x4_t __b) { |
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| 359 | return __builtin_arm_uxtab16(__a, __b); |
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| 360 | } |
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| 361 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
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| 362 | __uxtb16(int8x4_t __a) { |
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| 363 | return __builtin_arm_uxtb16(__a); |
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| 364 | } |
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| 365 | #endif |
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| 366 | |||
| 367 | /* 9.5.6 Parallel selection */ |
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| 368 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
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| 369 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 370 | __sel(uint8x4_t __a, uint8x4_t __b) { |
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| 371 | return __builtin_arm_sel(__a, __b); |
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| 372 | } |
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| 373 | #endif |
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| 374 | |||
| 375 | /* 9.5.7 Parallel 8-bit addition and subtraction */ |
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| 376 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
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| 377 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 378 | __qadd8(int8x4_t __a, int8x4_t __b) { |
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| 379 | return __builtin_arm_qadd8(__a, __b); |
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| 380 | } |
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| 381 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 382 | __qsub8(int8x4_t __a, int8x4_t __b) { |
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| 383 | return __builtin_arm_qsub8(__a, __b); |
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| 384 | } |
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| 385 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 386 | __sadd8(int8x4_t __a, int8x4_t __b) { |
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| 387 | return __builtin_arm_sadd8(__a, __b); |
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| 388 | } |
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| 389 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 390 | __shadd8(int8x4_t __a, int8x4_t __b) { |
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| 391 | return __builtin_arm_shadd8(__a, __b); |
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| 392 | } |
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| 393 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 394 | __shsub8(int8x4_t __a, int8x4_t __b) { |
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| 395 | return __builtin_arm_shsub8(__a, __b); |
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| 396 | } |
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| 397 | static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 398 | __ssub8(int8x4_t __a, int8x4_t __b) { |
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| 399 | return __builtin_arm_ssub8(__a, __b); |
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| 400 | } |
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| 401 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 402 | __uadd8(uint8x4_t __a, uint8x4_t __b) { |
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| 403 | return __builtin_arm_uadd8(__a, __b); |
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| 404 | } |
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| 405 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 406 | __uhadd8(uint8x4_t __a, uint8x4_t __b) { |
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| 407 | return __builtin_arm_uhadd8(__a, __b); |
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| 408 | } |
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| 409 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
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| 410 | __uhsub8(uint8x4_t __a, uint8x4_t __b) { |
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| 411 | return __builtin_arm_uhsub8(__a, __b); |
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| 412 | } |
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| 413 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
||
| 414 | __uqadd8(uint8x4_t __a, uint8x4_t __b) { |
||
| 415 | return __builtin_arm_uqadd8(__a, __b); |
||
| 416 | } |
||
| 417 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
||
| 418 | __uqsub8(uint8x4_t __a, uint8x4_t __b) { |
||
| 419 | return __builtin_arm_uqsub8(__a, __b); |
||
| 420 | } |
||
| 421 | static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) |
||
| 422 | __usub8(uint8x4_t __a, uint8x4_t __b) { |
||
| 423 | return __builtin_arm_usub8(__a, __b); |
||
| 424 | } |
||
| 425 | #endif |
||
| 426 | |||
| 427 | /* 9.5.8 Sum of 8-bit absolute differences */ |
||
| 428 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
||
| 429 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 430 | __usad8(uint8x4_t __a, uint8x4_t __b) { |
||
| 431 | return __builtin_arm_usad8(__a, __b); |
||
| 432 | } |
||
| 433 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 434 | __usada8(uint8x4_t __a, uint8x4_t __b, uint32_t __c) { |
||
| 435 | return __builtin_arm_usada8(__a, __b, __c); |
||
| 436 | } |
||
| 437 | #endif |
||
| 438 | |||
| 439 | /* 9.5.9 Parallel 16-bit addition and subtraction */ |
||
| 440 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
||
| 441 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 442 | __qadd16(int16x2_t __a, int16x2_t __b) { |
||
| 443 | return __builtin_arm_qadd16(__a, __b); |
||
| 444 | } |
||
| 445 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 446 | __qasx(int16x2_t __a, int16x2_t __b) { |
||
| 447 | return __builtin_arm_qasx(__a, __b); |
||
| 448 | } |
||
| 449 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 450 | __qsax(int16x2_t __a, int16x2_t __b) { |
||
| 451 | return __builtin_arm_qsax(__a, __b); |
||
| 452 | } |
||
| 453 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 454 | __qsub16(int16x2_t __a, int16x2_t __b) { |
||
| 455 | return __builtin_arm_qsub16(__a, __b); |
||
| 456 | } |
||
| 457 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 458 | __sadd16(int16x2_t __a, int16x2_t __b) { |
||
| 459 | return __builtin_arm_sadd16(__a, __b); |
||
| 460 | } |
||
| 461 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 462 | __sasx(int16x2_t __a, int16x2_t __b) { |
||
| 463 | return __builtin_arm_sasx(__a, __b); |
||
| 464 | } |
||
| 465 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 466 | __shadd16(int16x2_t __a, int16x2_t __b) { |
||
| 467 | return __builtin_arm_shadd16(__a, __b); |
||
| 468 | } |
||
| 469 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 470 | __shasx(int16x2_t __a, int16x2_t __b) { |
||
| 471 | return __builtin_arm_shasx(__a, __b); |
||
| 472 | } |
||
| 473 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 474 | __shsax(int16x2_t __a, int16x2_t __b) { |
||
| 475 | return __builtin_arm_shsax(__a, __b); |
||
| 476 | } |
||
| 477 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 478 | __shsub16(int16x2_t __a, int16x2_t __b) { |
||
| 479 | return __builtin_arm_shsub16(__a, __b); |
||
| 480 | } |
||
| 481 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 482 | __ssax(int16x2_t __a, int16x2_t __b) { |
||
| 483 | return __builtin_arm_ssax(__a, __b); |
||
| 484 | } |
||
| 485 | static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 486 | __ssub16(int16x2_t __a, int16x2_t __b) { |
||
| 487 | return __builtin_arm_ssub16(__a, __b); |
||
| 488 | } |
||
| 489 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 490 | __uadd16(uint16x2_t __a, uint16x2_t __b) { |
||
| 491 | return __builtin_arm_uadd16(__a, __b); |
||
| 492 | } |
||
| 493 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 494 | __uasx(uint16x2_t __a, uint16x2_t __b) { |
||
| 495 | return __builtin_arm_uasx(__a, __b); |
||
| 496 | } |
||
| 497 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 498 | __uhadd16(uint16x2_t __a, uint16x2_t __b) { |
||
| 499 | return __builtin_arm_uhadd16(__a, __b); |
||
| 500 | } |
||
| 501 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 502 | __uhasx(uint16x2_t __a, uint16x2_t __b) { |
||
| 503 | return __builtin_arm_uhasx(__a, __b); |
||
| 504 | } |
||
| 505 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 506 | __uhsax(uint16x2_t __a, uint16x2_t __b) { |
||
| 507 | return __builtin_arm_uhsax(__a, __b); |
||
| 508 | } |
||
| 509 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 510 | __uhsub16(uint16x2_t __a, uint16x2_t __b) { |
||
| 511 | return __builtin_arm_uhsub16(__a, __b); |
||
| 512 | } |
||
| 513 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 514 | __uqadd16(uint16x2_t __a, uint16x2_t __b) { |
||
| 515 | return __builtin_arm_uqadd16(__a, __b); |
||
| 516 | } |
||
| 517 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 518 | __uqasx(uint16x2_t __a, uint16x2_t __b) { |
||
| 519 | return __builtin_arm_uqasx(__a, __b); |
||
| 520 | } |
||
| 521 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 522 | __uqsax(uint16x2_t __a, uint16x2_t __b) { |
||
| 523 | return __builtin_arm_uqsax(__a, __b); |
||
| 524 | } |
||
| 525 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 526 | __uqsub16(uint16x2_t __a, uint16x2_t __b) { |
||
| 527 | return __builtin_arm_uqsub16(__a, __b); |
||
| 528 | } |
||
| 529 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 530 | __usax(uint16x2_t __a, uint16x2_t __b) { |
||
| 531 | return __builtin_arm_usax(__a, __b); |
||
| 532 | } |
||
| 533 | static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__)) |
||
| 534 | __usub16(uint16x2_t __a, uint16x2_t __b) { |
||
| 535 | return __builtin_arm_usub16(__a, __b); |
||
| 536 | } |
||
| 537 | #endif |
||
| 538 | |||
| 539 | /* 9.5.10 Parallel 16-bit multiplications */ |
||
| 540 | #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 |
||
| 541 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 542 | __smlad(int16x2_t __a, int16x2_t __b, int32_t __c) { |
||
| 543 | return __builtin_arm_smlad(__a, __b, __c); |
||
| 544 | } |
||
| 545 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 546 | __smladx(int16x2_t __a, int16x2_t __b, int32_t __c) { |
||
| 547 | return __builtin_arm_smladx(__a, __b, __c); |
||
| 548 | } |
||
| 549 | static __inline__ int64_t __attribute__((__always_inline__, __nodebug__)) |
||
| 550 | __smlald(int16x2_t __a, int16x2_t __b, int64_t __c) { |
||
| 551 | return __builtin_arm_smlald(__a, __b, __c); |
||
| 552 | } |
||
| 553 | static __inline__ int64_t __attribute__((__always_inline__, __nodebug__)) |
||
| 554 | __smlaldx(int16x2_t __a, int16x2_t __b, int64_t __c) { |
||
| 555 | return __builtin_arm_smlaldx(__a, __b, __c); |
||
| 556 | } |
||
| 557 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 558 | __smlsd(int16x2_t __a, int16x2_t __b, int32_t __c) { |
||
| 559 | return __builtin_arm_smlsd(__a, __b, __c); |
||
| 560 | } |
||
| 561 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 562 | __smlsdx(int16x2_t __a, int16x2_t __b, int32_t __c) { |
||
| 563 | return __builtin_arm_smlsdx(__a, __b, __c); |
||
| 564 | } |
||
| 565 | static __inline__ int64_t __attribute__((__always_inline__, __nodebug__)) |
||
| 566 | __smlsld(int16x2_t __a, int16x2_t __b, int64_t __c) { |
||
| 567 | return __builtin_arm_smlsld(__a, __b, __c); |
||
| 568 | } |
||
| 569 | static __inline__ int64_t __attribute__((__always_inline__, __nodebug__)) |
||
| 570 | __smlsldx(int16x2_t __a, int16x2_t __b, int64_t __c) { |
||
| 571 | return __builtin_arm_smlsldx(__a, __b, __c); |
||
| 572 | } |
||
| 573 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 574 | __smuad(int16x2_t __a, int16x2_t __b) { |
||
| 575 | return __builtin_arm_smuad(__a, __b); |
||
| 576 | } |
||
| 577 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 578 | __smuadx(int16x2_t __a, int16x2_t __b) { |
||
| 579 | return __builtin_arm_smuadx(__a, __b); |
||
| 580 | } |
||
| 581 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 582 | __smusd(int16x2_t __a, int16x2_t __b) { |
||
| 583 | return __builtin_arm_smusd(__a, __b); |
||
| 584 | } |
||
| 585 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) |
||
| 586 | __smusdx(int16x2_t __a, int16x2_t __b) { |
||
| 587 | return __builtin_arm_smusdx(__a, __b); |
||
| 588 | } |
||
| 589 | #endif |
||
| 590 | |||
| 591 | /* 9.7 CRC32 intrinsics */ |
||
| 592 | #if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) || \ |
||
| 593 | (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE) |
||
| 594 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 595 | __crc32b(uint32_t __a, uint8_t __b) { |
||
| 596 | return __builtin_arm_crc32b(__a, __b); |
||
| 597 | } |
||
| 598 | |||
| 599 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 600 | __crc32h(uint32_t __a, uint16_t __b) { |
||
| 601 | return __builtin_arm_crc32h(__a, __b); |
||
| 602 | } |
||
| 603 | |||
| 604 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 605 | __crc32w(uint32_t __a, uint32_t __b) { |
||
| 606 | return __builtin_arm_crc32w(__a, __b); |
||
| 607 | } |
||
| 608 | |||
| 609 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 610 | __crc32d(uint32_t __a, uint64_t __b) { |
||
| 611 | return __builtin_arm_crc32d(__a, __b); |
||
| 612 | } |
||
| 613 | |||
| 614 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 615 | __crc32cb(uint32_t __a, uint8_t __b) { |
||
| 616 | return __builtin_arm_crc32cb(__a, __b); |
||
| 617 | } |
||
| 618 | |||
| 619 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 620 | __crc32ch(uint32_t __a, uint16_t __b) { |
||
| 621 | return __builtin_arm_crc32ch(__a, __b); |
||
| 622 | } |
||
| 623 | |||
| 624 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 625 | __crc32cw(uint32_t __a, uint32_t __b) { |
||
| 626 | return __builtin_arm_crc32cw(__a, __b); |
||
| 627 | } |
||
| 628 | |||
| 629 | static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) |
||
| 630 | __crc32cd(uint32_t __a, uint64_t __b) { |
||
| 631 | return __builtin_arm_crc32cd(__a, __b); |
||
| 632 | } |
||
| 633 | #endif |
||
| 634 | |||
| 635 | /* Armv8.3-A Javascript conversion intrinsic */ |
||
| 636 | #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE |
||
| 637 | static __inline__ int32_t __attribute__((__always_inline__, __nodebug__, target("v8.3a"))) |
||
| 638 | __jcvt(double __a) { |
||
| 639 | return __builtin_arm_jcvt(__a); |
||
| 640 | } |
||
| 641 | #endif |
||
| 642 | |||
| 643 | /* Armv8.5-A FP rounding intrinsics */ |
||
| 644 | #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE |
||
| 645 | static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 646 | __rint32zf(float __a) { |
||
| 647 | return __builtin_arm_rint32zf(__a); |
||
| 648 | } |
||
| 649 | |||
| 650 | static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 651 | __rint32z(double __a) { |
||
| 652 | return __builtin_arm_rint32z(__a); |
||
| 653 | } |
||
| 654 | |||
| 655 | static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 656 | __rint64zf(float __a) { |
||
| 657 | return __builtin_arm_rint64zf(__a); |
||
| 658 | } |
||
| 659 | |||
| 660 | static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 661 | __rint64z(double __a) { |
||
| 662 | return __builtin_arm_rint64z(__a); |
||
| 663 | } |
||
| 664 | |||
| 665 | static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 666 | __rint32xf(float __a) { |
||
| 667 | return __builtin_arm_rint32xf(__a); |
||
| 668 | } |
||
| 669 | |||
| 670 | static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 671 | __rint32x(double __a) { |
||
| 672 | return __builtin_arm_rint32x(__a); |
||
| 673 | } |
||
| 674 | |||
| 675 | static __inline__ float __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 676 | __rint64xf(float __a) { |
||
| 677 | return __builtin_arm_rint64xf(__a); |
||
| 678 | } |
||
| 679 | |||
| 680 | static __inline__ double __attribute__((__always_inline__, __nodebug__, target("v8.5a"))) |
||
| 681 | __rint64x(double __a) { |
||
| 682 | return __builtin_arm_rint64x(__a); |
||
| 683 | } |
||
| 684 | #endif |
||
| 685 | |||
| 686 | /* Armv8.7-A load/store 64-byte intrinsics */ |
||
| 687 | #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE |
||
| 688 | typedef struct { |
||
| 689 | uint64_t val[8]; |
||
| 690 | } data512_t; |
||
| 691 | |||
| 692 | static __inline__ data512_t __attribute__((__always_inline__, __nodebug__, target("ls64"))) |
||
| 693 | __arm_ld64b(const void *__addr) { |
||
| 694 | data512_t __value; |
||
| 695 | __builtin_arm_ld64b(__addr, __value.val); |
||
| 696 | return __value; |
||
| 697 | } |
||
| 698 | static __inline__ void __attribute__((__always_inline__, __nodebug__, target("ls64"))) |
||
| 699 | __arm_st64b(void *__addr, data512_t __value) { |
||
| 700 | __builtin_arm_st64b(__addr, __value.val); |
||
| 701 | } |
||
| 702 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__, target("ls64"))) |
||
| 703 | __arm_st64bv(void *__addr, data512_t __value) { |
||
| 704 | return __builtin_arm_st64bv(__addr, __value.val); |
||
| 705 | } |
||
| 706 | static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__, target("ls64"))) |
||
| 707 | __arm_st64bv0(void *__addr, data512_t __value) { |
||
| 708 | return __builtin_arm_st64bv0(__addr, __value.val); |
||
| 709 | } |
||
| 710 | #endif |
||
| 711 | |||
| 712 | /* 10.1 Special register intrinsics */ |
||
| 713 | #define __arm_rsr(sysreg) __builtin_arm_rsr(sysreg) |
||
| 714 | #define __arm_rsr64(sysreg) __builtin_arm_rsr64(sysreg) |
||
| 715 | #define __arm_rsr128(sysreg) __builtin_arm_rsr128(sysreg) |
||
| 716 | #define __arm_rsrp(sysreg) __builtin_arm_rsrp(sysreg) |
||
| 717 | #define __arm_rsrf(sysreg) __builtin_bit_cast(float, __arm_rsr(sysreg)) |
||
| 718 | #define __arm_rsrf64(sysreg) __builtin_bit_cast(double, __arm_rsr64(sysreg)) |
||
| 719 | #define __arm_wsr(sysreg, v) __builtin_arm_wsr(sysreg, v) |
||
| 720 | #define __arm_wsr64(sysreg, v) __builtin_arm_wsr64(sysreg, v) |
||
| 721 | #define __arm_wsr128(sysreg, v) __builtin_arm_wsr128(sysreg, v) |
||
| 722 | #define __arm_wsrp(sysreg, v) __builtin_arm_wsrp(sysreg, v) |
||
| 723 | #define __arm_wsrf(sysreg, v) __arm_wsr(sysreg, __builtin_bit_cast(uint32_t, v)) |
||
| 724 | #define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg, __builtin_bit_cast(uint64_t, v)) |
||
| 725 | |||
| 726 | /* Memory Tagging Extensions (MTE) Intrinsics */ |
||
| 727 | #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE |
||
| 728 | #define __arm_mte_create_random_tag(__ptr, __mask) __builtin_arm_irg(__ptr, __mask) |
||
| 729 | #define __arm_mte_increment_tag(__ptr, __tag_offset) __builtin_arm_addg(__ptr, __tag_offset) |
||
| 730 | #define __arm_mte_exclude_tag(__ptr, __excluded) __builtin_arm_gmi(__ptr, __excluded) |
||
| 731 | #define __arm_mte_get_tag(__ptr) __builtin_arm_ldg(__ptr) |
||
| 732 | #define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr) |
||
| 733 | #define __arm_mte_ptrdiff(__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb) |
||
| 734 | |||
| 735 | /* Memory Operations Intrinsics */ |
||
| 736 | #define __arm_mops_memset_tag(__tagged_address, __value, __size) \ |
||
| 737 | __builtin_arm_mops_memset_tag(__tagged_address, __value, __size) |
||
| 738 | #endif |
||
| 739 | |||
| 740 | /* Transactional Memory Extension (TME) Intrinsics */ |
||
| 741 | #if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME |
||
| 742 | |||
| 743 | #define _TMFAILURE_REASON 0x00007fffu |
||
| 744 | #define _TMFAILURE_RTRY 0x00008000u |
||
| 745 | #define _TMFAILURE_CNCL 0x00010000u |
||
| 746 | #define _TMFAILURE_MEM 0x00020000u |
||
| 747 | #define _TMFAILURE_IMP 0x00040000u |
||
| 748 | #define _TMFAILURE_ERR 0x00080000u |
||
| 749 | #define _TMFAILURE_SIZE 0x00100000u |
||
| 750 | #define _TMFAILURE_NEST 0x00200000u |
||
| 751 | #define _TMFAILURE_DBG 0x00400000u |
||
| 752 | #define _TMFAILURE_INT 0x00800000u |
||
| 753 | #define _TMFAILURE_TRIVIAL 0x01000000u |
||
| 754 | |||
| 755 | #define __tstart() __builtin_arm_tstart() |
||
| 756 | #define __tcommit() __builtin_arm_tcommit() |
||
| 757 | #define __tcancel(__arg) __builtin_arm_tcancel(__arg) |
||
| 758 | #define __ttest() __builtin_arm_ttest() |
||
| 759 | |||
| 760 | #endif /* __ARM_FEATURE_TME */ |
||
| 761 | |||
| 762 | /* Armv8.5-A Random number generation intrinsics */ |
||
| 763 | #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE |
||
| 764 | static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand"))) |
||
| 765 | __rndr(uint64_t *__p) { |
||
| 766 | return __builtin_arm_rndr(__p); |
||
| 767 | } |
||
| 768 | static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand"))) |
||
| 769 | __rndrrs(uint64_t *__p) { |
||
| 770 | return __builtin_arm_rndrrs(__p); |
||
| 771 | } |
||
| 772 | #endif |
||
| 773 | |||
| 774 | #if defined(__cplusplus) |
||
| 775 | } |
||
| 776 | #endif |
||
| 777 | |||
| 778 | #endif /* __ARM_ACLE_H */ |