Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 14 | pmbaty | 1 | //===--------------------- Pipeline.h ---------------------------*- C++ -*-===// |
| 2 | // |
||
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
||
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
||
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
||
| 6 | // |
||
| 7 | //===----------------------------------------------------------------------===// |
||
| 8 | /// \file |
||
| 9 | /// |
||
| 10 | /// This file implements an ordered container of stages that simulate the |
||
| 11 | /// pipeline of a hardware backend. |
||
| 12 | /// |
||
| 13 | //===----------------------------------------------------------------------===// |
||
| 14 | |||
| 15 | #ifndef LLVM_MCA_PIPELINE_H |
||
| 16 | #define LLVM_MCA_PIPELINE_H |
||
| 17 | |||
| 18 | #include "llvm/MCA/Stages/Stage.h" |
||
| 19 | #include "llvm/Support/Error.h" |
||
| 20 | |||
| 21 | namespace llvm { |
||
| 22 | namespace mca { |
||
| 23 | |||
| 24 | class HWEventListener; |
||
| 25 | |||
| 26 | /// A pipeline for a specific subtarget. |
||
| 27 | /// |
||
| 28 | /// It emulates an out-of-order execution of instructions. Instructions are |
||
| 29 | /// fetched from a MCInst sequence managed by an initial 'Fetch' stage. |
||
| 30 | /// Instructions are firstly fetched, then dispatched to the schedulers, and |
||
| 31 | /// then executed. |
||
| 32 | /// |
||
| 33 | /// This class tracks the lifetime of an instruction from the moment where |
||
| 34 | /// it gets dispatched to the schedulers, to the moment where it finishes |
||
| 35 | /// executing and register writes are architecturally committed. |
||
| 36 | /// In particular, it monitors changes in the state of every instruction |
||
| 37 | /// in flight. |
||
| 38 | /// |
||
| 39 | /// Instructions are executed in a loop of iterations. The number of iterations |
||
| 40 | /// is defined by the SourceMgr object, which is managed by the initial stage |
||
| 41 | /// of the instruction pipeline. |
||
| 42 | /// |
||
| 43 | /// The Pipeline entry point is method 'run()' which executes cycles in a loop |
||
| 44 | /// until there are new instructions to dispatch, and not every instruction |
||
| 45 | /// has been retired. |
||
| 46 | /// |
||
| 47 | /// Internally, the Pipeline collects statistical information in the form of |
||
| 48 | /// histograms. For example, it tracks how the dispatch group size changes |
||
| 49 | /// over time. |
||
| 50 | class Pipeline { |
||
| 51 | Pipeline(const Pipeline &P) = delete; |
||
| 52 | Pipeline &operator=(const Pipeline &P) = delete; |
||
| 53 | |||
| 54 | enum class State { |
||
| 55 | Created, // Pipeline was just created. The default state. |
||
| 56 | Started, // Pipeline has started running. |
||
| 57 | Paused // Pipeline is paused. |
||
| 58 | }; |
||
| 59 | State CurrentState; |
||
| 60 | |||
| 61 | /// An ordered list of stages that define this instruction pipeline. |
||
| 62 | SmallVector<std::unique_ptr<Stage>, 8> Stages; |
||
| 63 | std::set<HWEventListener *> Listeners; |
||
| 64 | unsigned Cycles; |
||
| 65 | |||
| 66 | Error runCycle(); |
||
| 67 | bool hasWorkToProcess(); |
||
| 68 | void notifyCycleBegin(); |
||
| 69 | void notifyCycleEnd(); |
||
| 70 | |||
| 71 | public: |
||
| 72 | Pipeline() : CurrentState(State::Created), Cycles(0) {} |
||
| 73 | void appendStage(std::unique_ptr<Stage> S); |
||
| 74 | |||
| 75 | /// Returns the total number of simulated cycles. |
||
| 76 | Expected<unsigned> run(); |
||
| 77 | |||
| 78 | void addEventListener(HWEventListener *Listener); |
||
| 79 | |||
| 80 | /// Returns whether the pipeline is currently paused. |
||
| 81 | bool isPaused() const { return CurrentState == State::Paused; } |
||
| 82 | }; |
||
| 83 | } // namespace mca |
||
| 84 | } // namespace llvm |
||
| 85 | |||
| 86 | #endif // LLVM_MCA_PIPELINE_H |