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| Rev | Author | Line No. | Line |
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| 14 | pmbaty | 1 | //===- IntrinsicsLoongArch.td - Defines LoongArch intrinsics *- tablegen -*===// |
| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file defines all of the LoongArch-specific intrinsics. |
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| 10 | // |
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| 11 | //===----------------------------------------------------------------------===// |
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| 12 | |||
| 13 | let TargetPrefix = "loongarch" in { |
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| 14 | |||
| 15 | //===----------------------------------------------------------------------===// |
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| 16 | // Atomics |
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| 17 | |||
| 18 | // T @llvm.<name>.T.<p>(any*, T, T, T imm); |
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| 19 | class MaskedAtomicRMW<LLVMType itype> |
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| 20 | : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype], |
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| 21 | [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>; |
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| 22 | |||
| 23 | // We define 32-bit and 64-bit variants of the above, where T stands for i32 |
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| 24 | // or i64 respectively: |
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| 25 | multiclass MaskedAtomicRMWIntrinsics { |
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| 26 | // i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm); |
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| 27 | def _i32 : MaskedAtomicRMW<llvm_i32_ty>; |
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| 28 | // i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm); |
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| 29 | def _i64 : MaskedAtomicRMW<llvm_i64_ty>; |
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| 30 | } |
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| 31 | |||
| 32 | multiclass MaskedAtomicRMWFiveOpIntrinsics { |
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| 33 | // TODO: Support cmpxchg on LA32. |
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| 34 | // i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm); |
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| 35 | def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>; |
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| 36 | } |
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| 37 | |||
| 38 | defm int_loongarch_masked_atomicrmw_xchg : MaskedAtomicRMWIntrinsics; |
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| 39 | defm int_loongarch_masked_atomicrmw_add : MaskedAtomicRMWIntrinsics; |
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| 40 | defm int_loongarch_masked_atomicrmw_sub : MaskedAtomicRMWIntrinsics; |
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| 41 | defm int_loongarch_masked_atomicrmw_nand : MaskedAtomicRMWIntrinsics; |
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| 42 | defm int_loongarch_masked_atomicrmw_umax : MaskedAtomicRMWIntrinsics; |
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| 43 | defm int_loongarch_masked_atomicrmw_umin : MaskedAtomicRMWIntrinsics; |
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| 44 | defm int_loongarch_masked_atomicrmw_max : MaskedAtomicRMWFiveOpIntrinsics; |
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| 45 | defm int_loongarch_masked_atomicrmw_min : MaskedAtomicRMWFiveOpIntrinsics; |
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| 46 | |||
| 47 | // @llvm.loongarch.masked.cmpxchg.i64.<p>( |
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| 48 | // ptr addr, grlen cmpval, grlen newval, grlen mask, grlenimm ordering) |
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| 49 | defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics; |
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| 50 | |||
| 51 | //===----------------------------------------------------------------------===// |
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| 52 | // LoongArch BASE |
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| 53 | |||
| 54 | def int_loongarch_break : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; |
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| 55 | def int_loongarch_cacop_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], |
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| 56 | [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; |
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| 57 | def int_loongarch_cacop_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], |
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| 58 | [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; |
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| 59 | def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; |
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| 60 | def int_loongarch_ibar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; |
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| 61 | def int_loongarch_movfcsr2gr : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], |
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| 62 | [ImmArg<ArgIndex<0>>]>; |
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| 63 | def int_loongarch_movgr2fcsr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], |
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| 64 | [ImmArg<ArgIndex<0>>]>; |
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| 65 | def int_loongarch_syscall : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; |
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| 66 | |||
| 67 | def int_loongarch_crc_w_b_w : Intrinsic<[llvm_i32_ty], |
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| 68 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 69 | def int_loongarch_crc_w_h_w : Intrinsic<[llvm_i32_ty], |
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| 70 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 71 | def int_loongarch_crc_w_w_w : Intrinsic<[llvm_i32_ty], |
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| 72 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 73 | def int_loongarch_crc_w_d_w : Intrinsic<[llvm_i32_ty], |
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| 74 | [llvm_i64_ty, llvm_i32_ty]>; |
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| 75 | |||
| 76 | def int_loongarch_crcc_w_b_w : Intrinsic<[llvm_i32_ty], |
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| 77 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 78 | def int_loongarch_crcc_w_h_w : Intrinsic<[llvm_i32_ty], |
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| 79 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 80 | def int_loongarch_crcc_w_w_w : Intrinsic<[llvm_i32_ty], |
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| 81 | [llvm_i32_ty, llvm_i32_ty]>; |
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| 82 | def int_loongarch_crcc_w_d_w : Intrinsic<[llvm_i32_ty], |
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| 83 | [llvm_i64_ty, llvm_i32_ty]>; |
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| 84 | |||
| 85 | def int_loongarch_csrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], |
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| 86 | [ImmArg<ArgIndex<0>>]>; |
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| 87 | def int_loongarch_csrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty], |
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| 88 | [ImmArg<ArgIndex<0>>]>; |
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| 89 | def int_loongarch_csrwr_w : Intrinsic<[llvm_i32_ty], |
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| 90 | [llvm_i32_ty, llvm_i32_ty], |
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| 91 | [ImmArg<ArgIndex<1>>]>; |
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| 92 | def int_loongarch_csrwr_d : Intrinsic<[llvm_i64_ty], |
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| 93 | [llvm_i64_ty, llvm_i32_ty], |
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| 94 | [ImmArg<ArgIndex<1>>]>; |
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| 95 | def int_loongarch_csrxchg_w : Intrinsic<[llvm_i32_ty], |
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| 96 | [llvm_i32_ty, llvm_i32_ty, |
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| 97 | llvm_i32_ty], |
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| 98 | [ImmArg<ArgIndex<2>>]>; |
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| 99 | def int_loongarch_csrxchg_d : Intrinsic<[llvm_i64_ty], |
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| 100 | [llvm_i64_ty, llvm_i64_ty, |
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| 101 | llvm_i32_ty], |
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| 102 | [ImmArg<ArgIndex<2>>]>; |
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| 103 | |||
| 104 | def int_loongarch_iocsrrd_b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>; |
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| 105 | def int_loongarch_iocsrrd_h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>; |
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| 106 | def int_loongarch_iocsrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>; |
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| 107 | def int_loongarch_iocsrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty]>; |
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| 108 | |||
| 109 | def int_loongarch_iocsrwr_b : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>; |
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| 110 | def int_loongarch_iocsrwr_h : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>; |
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| 111 | def int_loongarch_iocsrwr_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>; |
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| 112 | def int_loongarch_iocsrwr_d : Intrinsic<[], [llvm_i64_ty, llvm_i32_ty]>; |
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| 113 | |||
| 114 | def int_loongarch_cpucfg : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>; |
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| 115 | |||
| 116 | def int_loongarch_asrtle_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>; |
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| 117 | def int_loongarch_asrtgt_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>; |
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| 118 | |||
| 119 | def int_loongarch_lddir_d : Intrinsic<[llvm_i64_ty], |
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| 120 | [llvm_i64_ty, llvm_i64_ty], |
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| 121 | [ImmArg<ArgIndex<1>>]>; |
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| 122 | def int_loongarch_ldpte_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], |
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| 123 | [ImmArg<ArgIndex<1>>]>; |
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| 124 | } // TargetPrefix = "loongarch" |