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| Rev | Author | Line No. | Line |
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| 14 | pmbaty | 1 | //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===// |
| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file contains the implementation for instruction scheduler function |
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| 10 | // pass registry (RegisterScheduler). |
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| 11 | // |
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| 12 | //===----------------------------------------------------------------------===// |
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| 13 | |||
| 14 | #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H |
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| 15 | #define LLVM_CODEGEN_SCHEDULERREGISTRY_H |
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| 16 | |||
| 17 | #include "llvm/CodeGen/MachinePassRegistry.h" |
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| 18 | #include "llvm/Support/CodeGen.h" |
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| 19 | |||
| 20 | namespace llvm { |
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| 21 | |||
| 22 | //===----------------------------------------------------------------------===// |
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| 23 | /// |
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| 24 | /// RegisterScheduler class - Track the registration of instruction schedulers. |
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| 25 | /// |
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| 26 | //===----------------------------------------------------------------------===// |
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| 27 | |||
| 28 | class ScheduleDAGSDNodes; |
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| 29 | class SelectionDAGISel; |
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| 30 | |||
| 31 | class RegisterScheduler |
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| 32 | : public MachinePassRegistryNode< |
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| 33 | ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level)> { |
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| 34 | public: |
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| 35 | using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*, |
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| 36 | CodeGenOpt::Level); |
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| 37 | |||
| 38 | static MachinePassRegistry<FunctionPassCtor> Registry; |
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| 39 | |||
| 40 | RegisterScheduler(const char *N, const char *D, FunctionPassCtor C) |
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| 41 | : MachinePassRegistryNode(N, D, C) { |
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| 42 | Registry.Add(this); |
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| 43 | } |
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| 44 | ~RegisterScheduler() { Registry.Remove(this); } |
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| 45 | |||
| 46 | |||
| 47 | // Accessors. |
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| 48 | RegisterScheduler *getNext() const { |
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| 49 | return (RegisterScheduler *)MachinePassRegistryNode::getNext(); |
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| 50 | } |
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| 51 | |||
| 52 | static RegisterScheduler *getList() { |
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| 53 | return (RegisterScheduler *)Registry.getList(); |
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| 54 | } |
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| 55 | |||
| 56 | static void setListener(MachinePassRegistryListener<FunctionPassCtor> *L) { |
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| 57 | Registry.setListener(L); |
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| 58 | } |
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| 59 | }; |
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| 60 | |||
| 61 | /// createBURRListDAGScheduler - This creates a bottom up register usage |
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| 62 | /// reduction list scheduler. |
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| 63 | ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, |
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| 64 | CodeGenOpt::Level OptLevel); |
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| 65 | |||
| 66 | /// createBURRListDAGScheduler - This creates a bottom up list scheduler that |
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| 67 | /// schedules nodes in source code order when possible. |
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| 68 | ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, |
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| 69 | CodeGenOpt::Level OptLevel); |
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| 70 | |||
| 71 | /// createHybridListDAGScheduler - This creates a bottom up register pressure |
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| 72 | /// aware list scheduler that make use of latency information to avoid stalls |
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| 73 | /// for long latency instructions in low register pressure mode. In high |
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| 74 | /// register pressure mode it schedules to reduce register pressure. |
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| 75 | ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS, |
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| 76 | CodeGenOpt::Level); |
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| 77 | |||
| 78 | /// createILPListDAGScheduler - This creates a bottom up register pressure |
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| 79 | /// aware list scheduler that tries to increase instruction level parallelism |
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| 80 | /// in low register pressure mode. In high register pressure mode it schedules |
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| 81 | /// to reduce register pressure. |
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| 82 | ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS, |
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| 83 | CodeGenOpt::Level); |
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| 84 | |||
| 85 | /// createFastDAGScheduler - This creates a "fast" scheduler. |
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| 86 | /// |
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| 87 | ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, |
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| 88 | CodeGenOpt::Level OptLevel); |
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| 89 | |||
| 90 | /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down |
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| 91 | /// DFA driven list scheduler with clustering heuristic to control |
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| 92 | /// register pressure. |
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| 93 | ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS, |
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| 94 | CodeGenOpt::Level OptLevel); |
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| 95 | /// createDefaultScheduler - This creates an instruction scheduler appropriate |
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| 96 | /// for the target. |
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| 97 | ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, |
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| 98 | CodeGenOpt::Level OptLevel); |
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| 99 | |||
| 100 | /// createDAGLinearizer - This creates a "no-scheduling" scheduler which |
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| 101 | /// linearize the DAG using topological order. |
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| 102 | ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS, |
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| 103 | CodeGenOpt::Level OptLevel); |
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| 104 | |||
| 105 | } // end namespace llvm |
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| 106 | |||
| 107 | #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H |